1 ;-------------------------------------------------------- 2 ; File Created by SDCC : free open source ANSI-C Compiler 3 ; Version 3.0.0 #6037 (Oct 31 2010) (Linux) 4 ; This file was generated Sun Feb 26 03:56:10 2012 5 ;-------------------------------------------------------- 6 .module spi1_master 7 .optsdcc -mmcs51 --model-medium 8 9 ;-------------------------------------------------------- 10 ; Public variables in this module 11 ;-------------------------------------------------------- 12 .globl _spi1MasterTransfer_PARM_3 13 .globl _spi1MasterTransfer_PARM_2 14 .globl _spi1MasterSetBitOrder_PARM_1 15 .globl _spi1MasterSetClockPhase_PARM_1 16 .globl _spi1MasterSetClockPolarity_PARM_1 17 .globl _spi1MasterInit 18 .globl _spi1MasterSetFrequency 19 .globl _spi1MasterSetClockPolarity 20 .globl _spi1MasterSetClockPhase 21 .globl _spi1MasterSetBitOrder 22 .globl _spi1MasterBusy 23 .globl _spi1MasterBytesLeft 24 .globl _spi1MasterTransfer 25 .globl _spi1MasterSendByte 26 .globl _spi1MasterReceiveByte 27 .globl _ISR_URX1 28 ;-------------------------------------------------------- 29 ; special function registers 30 ;-------------------------------------------------------- 31 .area RSEG (ABS,DATA) 0000 32 .org 0x0000 0080 33 Fspi1_master$P0$0$0 == 0x0080 0080 34 _P0 = 0x0080 0081 35 Fspi1_master$SP$0$0 == 0x0081 0081 36 _SP = 0x0081 0082 37 Fspi1_master$DPL0$0$0 == 0x0082 0082 38 _DPL0 = 0x0082 0083 39 Fspi1_master$DPH0$0$0 == 0x0083 0083 40 _DPH0 = 0x0083 0084 41 Fspi1_master$DPL1$0$0 == 0x0084 0084 42 _DPL1 = 0x0084 0085 43 Fspi1_master$DPH1$0$0 == 0x0085 0085 44 _DPH1 = 0x0085 0086 45 Fspi1_master$U0CSR$0$0 == 0x0086 0086 46 _U0CSR = 0x0086 0087 47 Fspi1_master$PCON$0$0 == 0x0087 0087 48 _PCON = 0x0087 0088 49 Fspi1_master$TCON$0$0 == 0x0088 0088 50 _TCON = 0x0088 0089 51 Fspi1_master$P0IFG$0$0 == 0x0089 0089 52 _P0IFG = 0x0089 008A 53 Fspi1_master$P1IFG$0$0 == 0x008a 008A 54 _P1IFG = 0x008a 008B 55 Fspi1_master$P2IFG$0$0 == 0x008b 008B 56 _P2IFG = 0x008b 008C 57 Fspi1_master$PICTL$0$0 == 0x008c 008C 58 _PICTL = 0x008c 008D 59 Fspi1_master$P1IEN$0$0 == 0x008d 008D 60 _P1IEN = 0x008d 008F 61 Fspi1_master$P0INP$0$0 == 0x008f 008F 62 _P0INP = 0x008f 0090 63 Fspi1_master$P1$0$0 == 0x0090 0090 64 _P1 = 0x0090 0091 65 Fspi1_master$RFIM$0$0 == 0x0091 0091 66 _RFIM = 0x0091 0092 67 Fspi1_master$DPS$0$0 == 0x0092 0092 68 _DPS = 0x0092 0093 69 Fspi1_master$MPAGE$0$0 == 0x0093 0093 70 _MPAGE = 0x0093 0095 71 Fspi1_master$ENDIAN$0$0 == 0x0095 0095 72 _ENDIAN = 0x0095 0098 73 Fspi1_master$S0CON$0$0 == 0x0098 0098 74 _S0CON = 0x0098 009A 75 Fspi1_master$IEN2$0$0 == 0x009a 009A 76 _IEN2 = 0x009a 009B 77 Fspi1_master$S1CON$0$0 == 0x009b 009B 78 _S1CON = 0x009b 009C 79 Fspi1_master$T2CT$0$0 == 0x009c 009C 80 _T2CT = 0x009c 009D 81 Fspi1_master$T2PR$0$0 == 0x009d 009D 82 _T2PR = 0x009d 009E 83 Fspi1_master$T2CTL$0$0 == 0x009e 009E 84 _T2CTL = 0x009e 00A0 85 Fspi1_master$P2$0$0 == 0x00a0 00A0 86 _P2 = 0x00a0 00A1 87 Fspi1_master$WORIRQ$0$0 == 0x00a1 00A1 88 _WORIRQ = 0x00a1 00A2 89 Fspi1_master$WORCTRL$0$0 == 0x00a2 00A2 90 _WORCTRL = 0x00a2 00A3 91 Fspi1_master$WOREVT0$0$0 == 0x00a3 00A3 92 _WOREVT0 = 0x00a3 00A4 93 Fspi1_master$WOREVT1$0$0 == 0x00a4 00A4 94 _WOREVT1 = 0x00a4 00A5 95 Fspi1_master$WORTIME0$0$0 == 0x00a5 00A5 96 _WORTIME0 = 0x00a5 00A6 97 Fspi1_master$WORTIME1$0$0 == 0x00a6 00A6 98 _WORTIME1 = 0x00a6 00A8 99 Fspi1_master$IEN0$0$0 == 0x00a8 00A8 100 _IEN0 = 0x00a8 00A9 101 Fspi1_master$IP0$0$0 == 0x00a9 00A9 102 _IP0 = 0x00a9 00AB 103 Fspi1_master$FWT$0$0 == 0x00ab 00AB 104 _FWT = 0x00ab 00AC 105 Fspi1_master$FADDRL$0$0 == 0x00ac 00AC 106 _FADDRL = 0x00ac 00AD 107 Fspi1_master$FADDRH$0$0 == 0x00ad 00AD 108 _FADDRH = 0x00ad 00AE 109 Fspi1_master$FCTL$0$0 == 0x00ae 00AE 110 _FCTL = 0x00ae 00AF 111 Fspi1_master$FWDATA$0$0 == 0x00af 00AF 112 _FWDATA = 0x00af 00B1 113 Fspi1_master$ENCDI$0$0 == 0x00b1 00B1 114 _ENCDI = 0x00b1 00B2 115 Fspi1_master$ENCDO$0$0 == 0x00b2 00B2 116 _ENCDO = 0x00b2 00B3 117 Fspi1_master$ENCCS$0$0 == 0x00b3 00B3 118 _ENCCS = 0x00b3 00B4 119 Fspi1_master$ADCCON1$0$0 == 0x00b4 00B4 120 _ADCCON1 = 0x00b4 00B5 121 Fspi1_master$ADCCON2$0$0 == 0x00b5 00B5 122 _ADCCON2 = 0x00b5 00B6 123 Fspi1_master$ADCCON3$0$0 == 0x00b6 00B6 124 _ADCCON3 = 0x00b6 00B8 125 Fspi1_master$IEN1$0$0 == 0x00b8 00B8 126 _IEN1 = 0x00b8 00B9 127 Fspi1_master$IP1$0$0 == 0x00b9 00B9 128 _IP1 = 0x00b9 00BA 129 Fspi1_master$ADCL$0$0 == 0x00ba 00BA 130 _ADCL = 0x00ba 00BB 131 Fspi1_master$ADCH$0$0 == 0x00bb 00BB 132 _ADCH = 0x00bb 00BC 133 Fspi1_master$RNDL$0$0 == 0x00bc 00BC 134 _RNDL = 0x00bc 00BD 135 Fspi1_master$RNDH$0$0 == 0x00bd 00BD 136 _RNDH = 0x00bd 00BE 137 Fspi1_master$SLEEP$0$0 == 0x00be 00BE 138 _SLEEP = 0x00be 00C0 139 Fspi1_master$IRCON$0$0 == 0x00c0 00C0 140 _IRCON = 0x00c0 00C1 141 Fspi1_master$U0DBUF$0$0 == 0x00c1 00C1 142 _U0DBUF = 0x00c1 00C2 143 Fspi1_master$U0BAUD$0$0 == 0x00c2 00C2 144 _U0BAUD = 0x00c2 00C4 145 Fspi1_master$U0UCR$0$0 == 0x00c4 00C4 146 _U0UCR = 0x00c4 00C5 147 Fspi1_master$U0GCR$0$0 == 0x00c5 00C5 148 _U0GCR = 0x00c5 00C6 149 Fspi1_master$CLKCON$0$0 == 0x00c6 00C6 150 _CLKCON = 0x00c6 00C7 151 Fspi1_master$MEMCTR$0$0 == 0x00c7 00C7 152 _MEMCTR = 0x00c7 00C9 153 Fspi1_master$WDCTL$0$0 == 0x00c9 00C9 154 _WDCTL = 0x00c9 00CA 155 Fspi1_master$T3CNT$0$0 == 0x00ca 00CA 156 _T3CNT = 0x00ca 00CB 157 Fspi1_master$T3CTL$0$0 == 0x00cb 00CB 158 _T3CTL = 0x00cb 00CC 159 Fspi1_master$T3CCTL0$0$0 == 0x00cc 00CC 160 _T3CCTL0 = 0x00cc 00CD 161 Fspi1_master$T3CC0$0$0 == 0x00cd 00CD 162 _T3CC0 = 0x00cd 00CE 163 Fspi1_master$T3CCTL1$0$0 == 0x00ce 00CE 164 _T3CCTL1 = 0x00ce 00CF 165 Fspi1_master$T3CC1$0$0 == 0x00cf 00CF 166 _T3CC1 = 0x00cf 00D0 167 Fspi1_master$PSW$0$0 == 0x00d0 00D0 168 _PSW = 0x00d0 00D1 169 Fspi1_master$DMAIRQ$0$0 == 0x00d1 00D1 170 _DMAIRQ = 0x00d1 00D2 171 Fspi1_master$DMA1CFGL$0$0 == 0x00d2 00D2 172 _DMA1CFGL = 0x00d2 00D3 173 Fspi1_master$DMA1CFGH$0$0 == 0x00d3 00D3 174 _DMA1CFGH = 0x00d3 00D4 175 Fspi1_master$DMA0CFGL$0$0 == 0x00d4 00D4 176 _DMA0CFGL = 0x00d4 00D5 177 Fspi1_master$DMA0CFGH$0$0 == 0x00d5 00D5 178 _DMA0CFGH = 0x00d5 00D6 179 Fspi1_master$DMAARM$0$0 == 0x00d6 00D6 180 _DMAARM = 0x00d6 00D7 181 Fspi1_master$DMAREQ$0$0 == 0x00d7 00D7 182 _DMAREQ = 0x00d7 00D8 183 Fspi1_master$TIMIF$0$0 == 0x00d8 00D8 184 _TIMIF = 0x00d8 00D9 185 Fspi1_master$RFD$0$0 == 0x00d9 00D9 186 _RFD = 0x00d9 00DA 187 Fspi1_master$T1CC0L$0$0 == 0x00da 00DA 188 _T1CC0L = 0x00da 00DB 189 Fspi1_master$T1CC0H$0$0 == 0x00db 00DB 190 _T1CC0H = 0x00db 00DC 191 Fspi1_master$T1CC1L$0$0 == 0x00dc 00DC 192 _T1CC1L = 0x00dc 00DD 193 Fspi1_master$T1CC1H$0$0 == 0x00dd 00DD 194 _T1CC1H = 0x00dd 00DE 195 Fspi1_master$T1CC2L$0$0 == 0x00de 00DE 196 _T1CC2L = 0x00de 00DF 197 Fspi1_master$T1CC2H$0$0 == 0x00df 00DF 198 _T1CC2H = 0x00df 00E0 199 Fspi1_master$ACC$0$0 == 0x00e0 00E0 200 _ACC = 0x00e0 00E1 201 Fspi1_master$RFST$0$0 == 0x00e1 00E1 202 _RFST = 0x00e1 00E2 203 Fspi1_master$T1CNTL$0$0 == 0x00e2 00E2 204 _T1CNTL = 0x00e2 00E3 205 Fspi1_master$T1CNTH$0$0 == 0x00e3 00E3 206 _T1CNTH = 0x00e3 00E4 207 Fspi1_master$T1CTL$0$0 == 0x00e4 00E4 208 _T1CTL = 0x00e4 00E5 209 Fspi1_master$T1CCTL0$0$0 == 0x00e5 00E5 210 _T1CCTL0 = 0x00e5 00E6 211 Fspi1_master$T1CCTL1$0$0 == 0x00e6 00E6 212 _T1CCTL1 = 0x00e6 00E7 213 Fspi1_master$T1CCTL2$0$0 == 0x00e7 00E7 214 _T1CCTL2 = 0x00e7 00E8 215 Fspi1_master$IRCON2$0$0 == 0x00e8 00E8 216 _IRCON2 = 0x00e8 00E9 217 Fspi1_master$RFIF$0$0 == 0x00e9 00E9 218 _RFIF = 0x00e9 00EA 219 Fspi1_master$T4CNT$0$0 == 0x00ea 00EA 220 _T4CNT = 0x00ea 00EB 221 Fspi1_master$T4CTL$0$0 == 0x00eb 00EB 222 _T4CTL = 0x00eb 00EC 223 Fspi1_master$T4CCTL0$0$0 == 0x00ec 00EC 224 _T4CCTL0 = 0x00ec 00ED 225 Fspi1_master$T4CC0$0$0 == 0x00ed 00ED 226 _T4CC0 = 0x00ed 00EE 227 Fspi1_master$T4CCTL1$0$0 == 0x00ee 00EE 228 _T4CCTL1 = 0x00ee 00EF 229 Fspi1_master$T4CC1$0$0 == 0x00ef 00EF 230 _T4CC1 = 0x00ef 00F0 231 Fspi1_master$B$0$0 == 0x00f0 00F0 232 _B = 0x00f0 00F1 233 Fspi1_master$PERCFG$0$0 == 0x00f1 00F1 234 _PERCFG = 0x00f1 00F2 235 Fspi1_master$ADCCFG$0$0 == 0x00f2 00F2 236 _ADCCFG = 0x00f2 00F3 237 Fspi1_master$P0SEL$0$0 == 0x00f3 00F3 238 _P0SEL = 0x00f3 00F4 239 Fspi1_master$P1SEL$0$0 == 0x00f4 00F4 240 _P1SEL = 0x00f4 00F5 241 Fspi1_master$P2SEL$0$0 == 0x00f5 00F5 242 _P2SEL = 0x00f5 00F6 243 Fspi1_master$P1INP$0$0 == 0x00f6 00F6 244 _P1INP = 0x00f6 00F7 245 Fspi1_master$P2INP$0$0 == 0x00f7 00F7 246 _P2INP = 0x00f7 00F8 247 Fspi1_master$U1CSR$0$0 == 0x00f8 00F8 248 _U1CSR = 0x00f8 00F9 249 Fspi1_master$U1DBUF$0$0 == 0x00f9 00F9 250 _U1DBUF = 0x00f9 00FA 251 Fspi1_master$U1BAUD$0$0 == 0x00fa 00FA 252 _U1BAUD = 0x00fa 00FB 253 Fspi1_master$U1UCR$0$0 == 0x00fb 00FB 254 _U1UCR = 0x00fb 00FC 255 Fspi1_master$U1GCR$0$0 == 0x00fc 00FC 256 _U1GCR = 0x00fc 00FD 257 Fspi1_master$P0DIR$0$0 == 0x00fd 00FD 258 _P0DIR = 0x00fd 00FE 259 Fspi1_master$P1DIR$0$0 == 0x00fe 00FE 260 _P1DIR = 0x00fe 00FF 261 Fspi1_master$P2DIR$0$0 == 0x00ff 00FF 262 _P2DIR = 0x00ff FFFFD5D4 263 Fspi1_master$DMA0CFG$0$0 == 0xffffd5d4 FFFFD5D4 264 _DMA0CFG = 0xffffd5d4 FFFFD3D2 265 Fspi1_master$DMA1CFG$0$0 == 0xffffd3d2 FFFFD3D2 266 _DMA1CFG = 0xffffd3d2 FFFFADAC 267 Fspi1_master$FADDR$0$0 == 0xffffadac FFFFADAC 268 _FADDR = 0xffffadac FFFFBBBA 269 Fspi1_master$ADC$0$0 == 0xffffbbba FFFFBBBA 270 _ADC = 0xffffbbba FFFFDBDA 271 Fspi1_master$T1CC0$0$0 == 0xffffdbda FFFFDBDA 272 _T1CC0 = 0xffffdbda FFFFDDDC 273 Fspi1_master$T1CC1$0$0 == 0xffffdddc FFFFDDDC 274 _T1CC1 = 0xffffdddc FFFFDFDE 275 Fspi1_master$T1CC2$0$0 == 0xffffdfde FFFFDFDE 276 _T1CC2 = 0xffffdfde 277 ;-------------------------------------------------------- 278 ; special function bits 279 ;-------------------------------------------------------- 280 .area RSEG (ABS,DATA) 0000 281 .org 0x0000 0080 282 Fspi1_master$P0_0$0$0 == 0x0080 0080 283 _P0_0 = 0x0080 0081 284 Fspi1_master$P0_1$0$0 == 0x0081 0081 285 _P0_1 = 0x0081 0082 286 Fspi1_master$P0_2$0$0 == 0x0082 0082 287 _P0_2 = 0x0082 0083 288 Fspi1_master$P0_3$0$0 == 0x0083 0083 289 _P0_3 = 0x0083 0084 290 Fspi1_master$P0_4$0$0 == 0x0084 0084 291 _P0_4 = 0x0084 0085 292 Fspi1_master$P0_5$0$0 == 0x0085 0085 293 _P0_5 = 0x0085 0086 294 Fspi1_master$P0_6$0$0 == 0x0086 0086 295 _P0_6 = 0x0086 0087 296 Fspi1_master$P0_7$0$0 == 0x0087 0087 297 _P0_7 = 0x0087 0088 298 Fspi1_master$_TCON_0$0$0 == 0x0088 0088 299 __TCON_0 = 0x0088 0089 300 Fspi1_master$RFTXRXIF$0$0 == 0x0089 0089 301 _RFTXRXIF = 0x0089 008A 302 Fspi1_master$_TCON_2$0$0 == 0x008a 008A 303 __TCON_2 = 0x008a 008B 304 Fspi1_master$URX0IF$0$0 == 0x008b 008B 305 _URX0IF = 0x008b 008C 306 Fspi1_master$_TCON_4$0$0 == 0x008c 008C 307 __TCON_4 = 0x008c 008D 308 Fspi1_master$ADCIF$0$0 == 0x008d 008D 309 _ADCIF = 0x008d 008E 310 Fspi1_master$_TCON_6$0$0 == 0x008e 008E 311 __TCON_6 = 0x008e 008F 312 Fspi1_master$URX1IF$0$0 == 0x008f 008F 313 _URX1IF = 0x008f 0090 314 Fspi1_master$P1_0$0$0 == 0x0090 0090 315 _P1_0 = 0x0090 0091 316 Fspi1_master$P1_1$0$0 == 0x0091 0091 317 _P1_1 = 0x0091 0092 318 Fspi1_master$P1_2$0$0 == 0x0092 0092 319 _P1_2 = 0x0092 0093 320 Fspi1_master$P1_3$0$0 == 0x0093 0093 321 _P1_3 = 0x0093 0094 322 Fspi1_master$P1_4$0$0 == 0x0094 0094 323 _P1_4 = 0x0094 0095 324 Fspi1_master$P1_5$0$0 == 0x0095 0095 325 _P1_5 = 0x0095 0096 326 Fspi1_master$P1_6$0$0 == 0x0096 0096 327 _P1_6 = 0x0096 0097 328 Fspi1_master$P1_7$0$0 == 0x0097 0097 329 _P1_7 = 0x0097 0098 330 Fspi1_master$ENCIF_0$0$0 == 0x0098 0098 331 _ENCIF_0 = 0x0098 0099 332 Fspi1_master$ENCIF_1$0$0 == 0x0099 0099 333 _ENCIF_1 = 0x0099 009A 334 Fspi1_master$_SOCON2$0$0 == 0x009a 009A 335 __SOCON2 = 0x009a 009B 336 Fspi1_master$_SOCON3$0$0 == 0x009b 009B 337 __SOCON3 = 0x009b 009C 338 Fspi1_master$_SOCON4$0$0 == 0x009c 009C 339 __SOCON4 = 0x009c 009D 340 Fspi1_master$_SOCON5$0$0 == 0x009d 009D 341 __SOCON5 = 0x009d 009E 342 Fspi1_master$_SOCON6$0$0 == 0x009e 009E 343 __SOCON6 = 0x009e 009F 344 Fspi1_master$_SOCON7$0$0 == 0x009f 009F 345 __SOCON7 = 0x009f 00A0 346 Fspi1_master$P2_0$0$0 == 0x00a0 00A0 347 _P2_0 = 0x00a0 00A1 348 Fspi1_master$P2_1$0$0 == 0x00a1 00A1 349 _P2_1 = 0x00a1 00A2 350 Fspi1_master$P2_2$0$0 == 0x00a2 00A2 351 _P2_2 = 0x00a2 00A3 352 Fspi1_master$P2_3$0$0 == 0x00a3 00A3 353 _P2_3 = 0x00a3 00A4 354 Fspi1_master$P2_4$0$0 == 0x00a4 00A4 355 _P2_4 = 0x00a4 00A5 356 Fspi1_master$P2_5$0$0 == 0x00a5 00A5 357 _P2_5 = 0x00a5 00A6 358 Fspi1_master$P2_6$0$0 == 0x00a6 00A6 359 _P2_6 = 0x00a6 00A7 360 Fspi1_master$P2_7$0$0 == 0x00a7 00A7 361 _P2_7 = 0x00a7 00A8 362 Fspi1_master$RFTXRXIE$0$0 == 0x00a8 00A8 363 _RFTXRXIE = 0x00a8 00A9 364 Fspi1_master$ADCIE$0$0 == 0x00a9 00A9 365 _ADCIE = 0x00a9 00AA 366 Fspi1_master$URX0IE$0$0 == 0x00aa 00AA 367 _URX0IE = 0x00aa 00AB 368 Fspi1_master$URX1IE$0$0 == 0x00ab 00AB 369 _URX1IE = 0x00ab 00AC 370 Fspi1_master$ENCIE$0$0 == 0x00ac 00AC 371 _ENCIE = 0x00ac 00AD 372 Fspi1_master$STIE$0$0 == 0x00ad 00AD 373 _STIE = 0x00ad 00AE 374 Fspi1_master$_IEN06$0$0 == 0x00ae 00AE 375 __IEN06 = 0x00ae 00AF 376 Fspi1_master$EA$0$0 == 0x00af 00AF 377 _EA = 0x00af 00B8 378 Fspi1_master$DMAIE$0$0 == 0x00b8 00B8 379 _DMAIE = 0x00b8 00B9 380 Fspi1_master$T1IE$0$0 == 0x00b9 00B9 381 _T1IE = 0x00b9 00BA 382 Fspi1_master$T2IE$0$0 == 0x00ba 00BA 383 _T2IE = 0x00ba 00BB 384 Fspi1_master$T3IE$0$0 == 0x00bb 00BB 385 _T3IE = 0x00bb 00BC 386 Fspi1_master$T4IE$0$0 == 0x00bc 00BC 387 _T4IE = 0x00bc 00BD 388 Fspi1_master$P0IE$0$0 == 0x00bd 00BD 389 _P0IE = 0x00bd 00BE 390 Fspi1_master$_IEN16$0$0 == 0x00be 00BE 391 __IEN16 = 0x00be 00BF 392 Fspi1_master$_IEN17$0$0 == 0x00bf 00BF 393 __IEN17 = 0x00bf 00C0 394 Fspi1_master$DMAIF$0$0 == 0x00c0 00C0 395 _DMAIF = 0x00c0 00C1 396 Fspi1_master$T1IF$0$0 == 0x00c1 00C1 397 _T1IF = 0x00c1 00C2 398 Fspi1_master$T2IF$0$0 == 0x00c2 00C2 399 _T2IF = 0x00c2 00C3 400 Fspi1_master$T3IF$0$0 == 0x00c3 00C3 401 _T3IF = 0x00c3 00C4 402 Fspi1_master$T4IF$0$0 == 0x00c4 00C4 403 _T4IF = 0x00c4 00C5 404 Fspi1_master$P0IF$0$0 == 0x00c5 00C5 405 _P0IF = 0x00c5 00C6 406 Fspi1_master$_IRCON6$0$0 == 0x00c6 00C6 407 __IRCON6 = 0x00c6 00C7 408 Fspi1_master$STIF$0$0 == 0x00c7 00C7 409 _STIF = 0x00c7 00D0 410 Fspi1_master$P$0$0 == 0x00d0 00D0 411 _P = 0x00d0 00D1 412 Fspi1_master$F1$0$0 == 0x00d1 00D1 413 _F1 = 0x00d1 00D2 414 Fspi1_master$OV$0$0 == 0x00d2 00D2 415 _OV = 0x00d2 00D3 416 Fspi1_master$RS0$0$0 == 0x00d3 00D3 417 _RS0 = 0x00d3 00D4 418 Fspi1_master$RS1$0$0 == 0x00d4 00D4 419 _RS1 = 0x00d4 00D5 420 Fspi1_master$F0$0$0 == 0x00d5 00D5 421 _F0 = 0x00d5 00D6 422 Fspi1_master$AC$0$0 == 0x00d6 00D6 423 _AC = 0x00d6 00D7 424 Fspi1_master$CY$0$0 == 0x00d7 00D7 425 _CY = 0x00d7 00D8 426 Fspi1_master$T3OVFIF$0$0 == 0x00d8 00D8 427 _T3OVFIF = 0x00d8 00D9 428 Fspi1_master$T3CH0IF$0$0 == 0x00d9 00D9 429 _T3CH0IF = 0x00d9 00DA 430 Fspi1_master$T3CH1IF$0$0 == 0x00da 00DA 431 _T3CH1IF = 0x00da 00DB 432 Fspi1_master$T4OVFIF$0$0 == 0x00db 00DB 433 _T4OVFIF = 0x00db 00DC 434 Fspi1_master$T4CH0IF$0$0 == 0x00dc 00DC 435 _T4CH0IF = 0x00dc 00DD 436 Fspi1_master$T4CH1IF$0$0 == 0x00dd 00DD 437 _T4CH1IF = 0x00dd 00DE 438 Fspi1_master$OVFIM$0$0 == 0x00de 00DE 439 _OVFIM = 0x00de 00DF 440 Fspi1_master$_TIMIF7$0$0 == 0x00df 00DF 441 __TIMIF7 = 0x00df 00E0 442 Fspi1_master$ACC_0$0$0 == 0x00e0 00E0 443 _ACC_0 = 0x00e0 00E1 444 Fspi1_master$ACC_1$0$0 == 0x00e1 00E1 445 _ACC_1 = 0x00e1 00E2 446 Fspi1_master$ACC_2$0$0 == 0x00e2 00E2 447 _ACC_2 = 0x00e2 00E3 448 Fspi1_master$ACC_3$0$0 == 0x00e3 00E3 449 _ACC_3 = 0x00e3 00E4 450 Fspi1_master$ACC_4$0$0 == 0x00e4 00E4 451 _ACC_4 = 0x00e4 00E5 452 Fspi1_master$ACC_5$0$0 == 0x00e5 00E5 453 _ACC_5 = 0x00e5 00E6 454 Fspi1_master$ACC_6$0$0 == 0x00e6 00E6 455 _ACC_6 = 0x00e6 00E7 456 Fspi1_master$ACC_7$0$0 == 0x00e7 00E7 457 _ACC_7 = 0x00e7 00E8 458 Fspi1_master$P2IF$0$0 == 0x00e8 00E8 459 _P2IF = 0x00e8 00E9 460 Fspi1_master$UTX0IF$0$0 == 0x00e9 00E9 461 _UTX0IF = 0x00e9 00EA 462 Fspi1_master$UTX1IF$0$0 == 0x00ea 00EA 463 _UTX1IF = 0x00ea 00EB 464 Fspi1_master$P1IF$0$0 == 0x00eb 00EB 465 _P1IF = 0x00eb 00EC 466 Fspi1_master$WDTIF$0$0 == 0x00ec 00EC 467 _WDTIF = 0x00ec 00ED 468 Fspi1_master$_IRCON25$0$0 == 0x00ed 00ED 469 __IRCON25 = 0x00ed 00EE 470 Fspi1_master$_IRCON26$0$0 == 0x00ee 00EE 471 __IRCON26 = 0x00ee 00EF 472 Fspi1_master$_IRCON27$0$0 == 0x00ef 00EF 473 __IRCON27 = 0x00ef 00F0 474 Fspi1_master$B_0$0$0 == 0x00f0 00F0 475 _B_0 = 0x00f0 00F1 476 Fspi1_master$B_1$0$0 == 0x00f1 00F1 477 _B_1 = 0x00f1 00F2 478 Fspi1_master$B_2$0$0 == 0x00f2 00F2 479 _B_2 = 0x00f2 00F3 480 Fspi1_master$B_3$0$0 == 0x00f3 00F3 481 _B_3 = 0x00f3 00F4 482 Fspi1_master$B_4$0$0 == 0x00f4 00F4 483 _B_4 = 0x00f4 00F5 484 Fspi1_master$B_5$0$0 == 0x00f5 00F5 485 _B_5 = 0x00f5 00F6 486 Fspi1_master$B_6$0$0 == 0x00f6 00F6 487 _B_6 = 0x00f6 00F7 488 Fspi1_master$B_7$0$0 == 0x00f7 00F7 489 _B_7 = 0x00f7 00F8 490 Fspi1_master$U1ACTIVE$0$0 == 0x00f8 00F8 491 _U1ACTIVE = 0x00f8 00F9 492 Fspi1_master$U1TX_BYTE$0$0 == 0x00f9 00F9 493 _U1TX_BYTE = 0x00f9 00FA 494 Fspi1_master$U1RX_BYTE$0$0 == 0x00fa 00FA 495 _U1RX_BYTE = 0x00fa 00FB 496 Fspi1_master$U1ERR$0$0 == 0x00fb 00FB 497 _U1ERR = 0x00fb 00FC 498 Fspi1_master$U1FE$0$0 == 0x00fc 00FC 499 _U1FE = 0x00fc 00FD 500 Fspi1_master$U1SLAVE$0$0 == 0x00fd 00FD 501 _U1SLAVE = 0x00fd 00FE 502 Fspi1_master$U1RE$0$0 == 0x00fe 00FE 503 _U1RE = 0x00fe 00FF 504 Fspi1_master$U1MODE$0$0 == 0x00ff 00FF 505 _U1MODE = 0x00ff 506 ;-------------------------------------------------------- 507 ; overlayable register banks 508 ;-------------------------------------------------------- 509 .area REG_BANK_0 (REL,OVR,DATA) 0000 510 .ds 8 511 ;-------------------------------------------------------- 512 ; internal ram data 513 ;-------------------------------------------------------- 514 .area DSEG (DATA) 0000 515 Fspi1_master$txPointer$0$0==. 0000 516 _txPointer: 0000 517 .ds 2 0002 518 Fspi1_master$rxPointer$0$0==. 0002 519 _rxPointer: 0002 520 .ds 2 0004 521 Fspi1_master$bytesLeft$0$0==. 0004 522 _bytesLeft: 0004 523 .ds 2 0006 524 Lspi1MasterSetFrequency$sloc0$1$0==. 0006 525 _spi1MasterSetFrequency_sloc0_1_0: 0006 526 .ds 4 527 ;-------------------------------------------------------- 528 ; overlayable items in internal ram 529 ;-------------------------------------------------------- 530 .area OSEG (OVR,DATA) 531 ;-------------------------------------------------------- 532 ; indirectly addressable internal ram data 533 ;-------------------------------------------------------- 534 .area ISEG (DATA) 535 ;-------------------------------------------------------- 536 ; absolute internal ram data 537 ;-------------------------------------------------------- 538 .area IABS (ABS,DATA) 539 .area IABS (ABS,DATA) 540 ;-------------------------------------------------------- 541 ; bit data 542 ;-------------------------------------------------------- 543 .area BSEG (BIT) 0000 544 Lspi1MasterSetClockPolarity$polarity$1$1==. 0000 545 _spi1MasterSetClockPolarity_PARM_1: 0000 546 .ds 1 0001 547 Lspi1MasterSetClockPhase$phase$1$1==. 0001 548 _spi1MasterSetClockPhase_PARM_1: 0001 549 .ds 1 0002 550 Lspi1MasterSetBitOrder$bitOrder$1$1==. 0002 551 _spi1MasterSetBitOrder_PARM_1: 0002 552 .ds 1 553 ;-------------------------------------------------------- 554 ; paged external ram data 555 ;-------------------------------------------------------- 556 .area PSEG (PAG,XDATA) 0000 557 Lspi1MasterTransfer$rxBuffer$1$1==. 0000 558 _spi1MasterTransfer_PARM_2: 0000 559 .ds 2 0002 560 Lspi1MasterTransfer$size$1$1==. 0002 561 _spi1MasterTransfer_PARM_3: 0002 562 .ds 2 563 ;-------------------------------------------------------- 564 ; external ram data 565 ;-------------------------------------------------------- 566 .area XSEG (XDATA) DF00 567 Fspi1_master$SYNC1$0$0 == 0xdf00 DF00 568 _SYNC1 = 0xdf00 DF01 569 Fspi1_master$SYNC0$0$0 == 0xdf01 DF01 570 _SYNC0 = 0xdf01 DF02 571 Fspi1_master$PKTLEN$0$0 == 0xdf02 DF02 572 _PKTLEN = 0xdf02 DF03 573 Fspi1_master$PKTCTRL1$0$0 == 0xdf03 DF03 574 _PKTCTRL1 = 0xdf03 DF04 575 Fspi1_master$PKTCTRL0$0$0 == 0xdf04 DF04 576 _PKTCTRL0 = 0xdf04 DF05 577 Fspi1_master$ADDR$0$0 == 0xdf05 DF05 578 _ADDR = 0xdf05 DF06 579 Fspi1_master$CHANNR$0$0 == 0xdf06 DF06 580 _CHANNR = 0xdf06 DF07 581 Fspi1_master$FSCTRL1$0$0 == 0xdf07 DF07 582 _FSCTRL1 = 0xdf07 DF08 583 Fspi1_master$FSCTRL0$0$0 == 0xdf08 DF08 584 _FSCTRL0 = 0xdf08 DF09 585 Fspi1_master$FREQ2$0$0 == 0xdf09 DF09 586 _FREQ2 = 0xdf09 DF0A 587 Fspi1_master$FREQ1$0$0 == 0xdf0a DF0A 588 _FREQ1 = 0xdf0a DF0B 589 Fspi1_master$FREQ0$0$0 == 0xdf0b DF0B 590 _FREQ0 = 0xdf0b DF0C 591 Fspi1_master$MDMCFG4$0$0 == 0xdf0c DF0C 592 _MDMCFG4 = 0xdf0c DF0D 593 Fspi1_master$MDMCFG3$0$0 == 0xdf0d DF0D 594 _MDMCFG3 = 0xdf0d DF0E 595 Fspi1_master$MDMCFG2$0$0 == 0xdf0e DF0E 596 _MDMCFG2 = 0xdf0e DF0F 597 Fspi1_master$MDMCFG1$0$0 == 0xdf0f DF0F 598 _MDMCFG1 = 0xdf0f DF10 599 Fspi1_master$MDMCFG0$0$0 == 0xdf10 DF10 600 _MDMCFG0 = 0xdf10 DF11 601 Fspi1_master$DEVIATN$0$0 == 0xdf11 DF11 602 _DEVIATN = 0xdf11 DF12 603 Fspi1_master$MCSM2$0$0 == 0xdf12 DF12 604 _MCSM2 = 0xdf12 DF13 605 Fspi1_master$MCSM1$0$0 == 0xdf13 DF13 606 _MCSM1 = 0xdf13 DF14 607 Fspi1_master$MCSM0$0$0 == 0xdf14 DF14 608 _MCSM0 = 0xdf14 DF15 609 Fspi1_master$FOCCFG$0$0 == 0xdf15 DF15 610 _FOCCFG = 0xdf15 DF16 611 Fspi1_master$BSCFG$0$0 == 0xdf16 DF16 612 _BSCFG = 0xdf16 DF17 613 Fspi1_master$AGCCTRL2$0$0 == 0xdf17 DF17 614 _AGCCTRL2 = 0xdf17 DF18 615 Fspi1_master$AGCCTRL1$0$0 == 0xdf18 DF18 616 _AGCCTRL1 = 0xdf18 DF19 617 Fspi1_master$AGCCTRL0$0$0 == 0xdf19 DF19 618 _AGCCTRL0 = 0xdf19 DF1A 619 Fspi1_master$FREND1$0$0 == 0xdf1a DF1A 620 _FREND1 = 0xdf1a DF1B 621 Fspi1_master$FREND0$0$0 == 0xdf1b DF1B 622 _FREND0 = 0xdf1b DF1C 623 Fspi1_master$FSCAL3$0$0 == 0xdf1c DF1C 624 _FSCAL3 = 0xdf1c DF1D 625 Fspi1_master$FSCAL2$0$0 == 0xdf1d DF1D 626 _FSCAL2 = 0xdf1d DF1E 627 Fspi1_master$FSCAL1$0$0 == 0xdf1e DF1E 628 _FSCAL1 = 0xdf1e DF1F 629 Fspi1_master$FSCAL0$0$0 == 0xdf1f DF1F 630 _FSCAL0 = 0xdf1f DF23 631 Fspi1_master$TEST2$0$0 == 0xdf23 DF23 632 _TEST2 = 0xdf23 DF24 633 Fspi1_master$TEST1$0$0 == 0xdf24 DF24 634 _TEST1 = 0xdf24 DF25 635 Fspi1_master$TEST0$0$0 == 0xdf25 DF25 636 _TEST0 = 0xdf25 DF2E 637 Fspi1_master$PA_TABLE0$0$0 == 0xdf2e DF2E 638 _PA_TABLE0 = 0xdf2e DF2F 639 Fspi1_master$IOCFG2$0$0 == 0xdf2f DF2F 640 _IOCFG2 = 0xdf2f DF30 641 Fspi1_master$IOCFG1$0$0 == 0xdf30 DF30 642 _IOCFG1 = 0xdf30 DF31 643 Fspi1_master$IOCFG0$0$0 == 0xdf31 DF31 644 _IOCFG0 = 0xdf31 DF36 645 Fspi1_master$PARTNUM$0$0 == 0xdf36 DF36 646 _PARTNUM = 0xdf36 DF37 647 Fspi1_master$VERSION$0$0 == 0xdf37 DF37 648 _VERSION = 0xdf37 DF38 649 Fspi1_master$FREQEST$0$0 == 0xdf38 DF38 650 _FREQEST = 0xdf38 DF39 651 Fspi1_master$LQI$0$0 == 0xdf39 DF39 652 _LQI = 0xdf39 DF3A 653 Fspi1_master$RSSI$0$0 == 0xdf3a DF3A 654 _RSSI = 0xdf3a DF3B 655 Fspi1_master$MARCSTATE$0$0 == 0xdf3b DF3B 656 _MARCSTATE = 0xdf3b DF3C 657 Fspi1_master$PKTSTATUS$0$0 == 0xdf3c DF3C 658 _PKTSTATUS = 0xdf3c DF3D 659 Fspi1_master$VCO_VC_DAC$0$0 == 0xdf3d DF3D 660 _VCO_VC_DAC = 0xdf3d DF40 661 Fspi1_master$I2SCFG0$0$0 == 0xdf40 DF40 662 _I2SCFG0 = 0xdf40 DF41 663 Fspi1_master$I2SCFG1$0$0 == 0xdf41 DF41 664 _I2SCFG1 = 0xdf41 DF42 665 Fspi1_master$I2SDATL$0$0 == 0xdf42 DF42 666 _I2SDATL = 0xdf42 DF43 667 Fspi1_master$I2SDATH$0$0 == 0xdf43 DF43 668 _I2SDATH = 0xdf43 DF44 669 Fspi1_master$I2SWCNT$0$0 == 0xdf44 DF44 670 _I2SWCNT = 0xdf44 DF45 671 Fspi1_master$I2SSTAT$0$0 == 0xdf45 DF45 672 _I2SSTAT = 0xdf45 DF46 673 Fspi1_master$I2SCLKF0$0$0 == 0xdf46 DF46 674 _I2SCLKF0 = 0xdf46 DF47 675 Fspi1_master$I2SCLKF1$0$0 == 0xdf47 DF47 676 _I2SCLKF1 = 0xdf47 DF48 677 Fspi1_master$I2SCLKF2$0$0 == 0xdf48 DF48 678 _I2SCLKF2 = 0xdf48 DE00 679 Fspi1_master$USBADDR$0$0 == 0xde00 DE00 680 _USBADDR = 0xde00 DE01 681 Fspi1_master$USBPOW$0$0 == 0xde01 DE01 682 _USBPOW = 0xde01 DE02 683 Fspi1_master$USBIIF$0$0 == 0xde02 DE02 684 _USBIIF = 0xde02 DE04 685 Fspi1_master$USBOIF$0$0 == 0xde04 DE04 686 _USBOIF = 0xde04 DE06 687 Fspi1_master$USBCIF$0$0 == 0xde06 DE06 688 _USBCIF = 0xde06 DE07 689 Fspi1_master$USBIIE$0$0 == 0xde07 DE07 690 _USBIIE = 0xde07 DE09 691 Fspi1_master$USBOIE$0$0 == 0xde09 DE09 692 _USBOIE = 0xde09 DE0B 693 Fspi1_master$USBCIE$0$0 == 0xde0b DE0B 694 _USBCIE = 0xde0b DE0C 695 Fspi1_master$USBFRML$0$0 == 0xde0c DE0C 696 _USBFRML = 0xde0c DE0D 697 Fspi1_master$USBFRMH$0$0 == 0xde0d DE0D 698 _USBFRMH = 0xde0d DE0E 699 Fspi1_master$USBINDEX$0$0 == 0xde0e DE0E 700 _USBINDEX = 0xde0e DE10 701 Fspi1_master$USBMAXI$0$0 == 0xde10 DE10 702 _USBMAXI = 0xde10 DE11 703 Fspi1_master$USBCSIL$0$0 == 0xde11 DE11 704 _USBCSIL = 0xde11 DE12 705 Fspi1_master$USBCSIH$0$0 == 0xde12 DE12 706 _USBCSIH = 0xde12 DE13 707 Fspi1_master$USBMAXO$0$0 == 0xde13 DE13 708 _USBMAXO = 0xde13 DE14 709 Fspi1_master$USBCSOL$0$0 == 0xde14 DE14 710 _USBCSOL = 0xde14 DE15 711 Fspi1_master$USBCSOH$0$0 == 0xde15 DE15 712 _USBCSOH = 0xde15 DE16 713 Fspi1_master$USBCNTL$0$0 == 0xde16 DE16 714 _USBCNTL = 0xde16 DE17 715 Fspi1_master$USBCNTH$0$0 == 0xde17 DE17 716 _USBCNTH = 0xde17 DE20 717 Fspi1_master$USBF0$0$0 == 0xde20 DE20 718 _USBF0 = 0xde20 DE22 719 Fspi1_master$USBF1$0$0 == 0xde22 DE22 720 _USBF1 = 0xde22 DE24 721 Fspi1_master$USBF2$0$0 == 0xde24 DE24 722 _USBF2 = 0xde24 DE26 723 Fspi1_master$USBF3$0$0 == 0xde26 DE26 724 _USBF3 = 0xde26 DE28 725 Fspi1_master$USBF4$0$0 == 0xde28 DE28 726 _USBF4 = 0xde28 DE2A 727 Fspi1_master$USBF5$0$0 == 0xde2a DE2A 728 _USBF5 = 0xde2a 0000 729 Lspi1MasterSendByte$byte$1$1==. 0000 730 _spi1MasterSendByte_byte_1_1: 0000 731 .ds 1 0001 732 Lspi1MasterSendByte$rxByte$1$1==. 0001 733 _spi1MasterSendByte_rxByte_1_1: 0001 734 .ds 1 735 ;-------------------------------------------------------- 736 ; absolute external ram data 737 ;-------------------------------------------------------- 738 .area XABS (ABS,XDATA) 739 ;-------------------------------------------------------- 740 ; external initialized ram data 741 ;-------------------------------------------------------- 742 .area XISEG (XDATA) 743 .area HOME (CODE) 744 .area GSINIT0 (CODE) 745 .area GSINIT1 (CODE) 746 .area GSINIT2 (CODE) 747 .area GSINIT3 (CODE) 748 .area GSINIT4 (CODE) 749 .area GSINIT5 (CODE) 750 .area GSINIT (CODE) 751 .area GSFINAL (CODE) 752 .area CSEG (CODE) 753 ;-------------------------------------------------------- 754 ; global & static initialisations 755 ;-------------------------------------------------------- 756 .area HOME (CODE) 757 .area GSINIT (CODE) 758 .area GSFINAL (CODE) 759 .area GSINIT (CODE) 0000 760 G$ISR_URX1$0$0 ==. 0000 761 C$spi1_master.c$55$1$1 ==. 762 ; libraries/src/spi_master/spi1_master.c:55: static volatile const uint8 XDATA * DATA txPointer = 0; 0000 E4 763 clr a 0001 F5*00 764 mov _txPointer,a 0003 F5*01 765 mov (_txPointer + 1),a 0005 766 G$ISR_URX1$0$0 ==. 0005 767 C$spi1_master.c$58$1$1 ==. 768 ; libraries/src/spi_master/spi1_master.c:58: static volatile uint8 XDATA * DATA rxPointer = 0; 0005 E4 769 clr a 0006 F5*02 770 mov _rxPointer,a 0008 F5*03 771 mov (_rxPointer + 1),a 000A 772 G$ISR_URX1$0$0 ==. 000A 773 C$spi1_master.c$61$1$1 ==. 774 ; libraries/src/spi_master/spi1_master.c:61: static volatile uint16 DATA bytesLeft = 0; 000A E4 775 clr a 000B F5*04 776 mov _bytesLeft,a 000D F5*05 777 mov (_bytesLeft + 1),a 778 ;-------------------------------------------------------- 779 ; Home 780 ;-------------------------------------------------------- 781 .area HOME (CODE) 782 .area HOME (CODE) 783 ;-------------------------------------------------------- 784 ; code 785 ;-------------------------------------------------------- 786 .area CSEG (CODE) 787 ;------------------------------------------------------------ 788 ;Allocation info for local variables in function 'spi1MasterInit' 789 ;------------------------------------------------------------ 790 ;------------------------------------------------------------ 0000 791 G$spi1MasterInit$0$0 ==. 0000 792 C$spi1_master.c$63$0$0 ==. 793 ; libraries/src/spi_master/spi1_master.c:63: void spiNMasterInit(void) 794 ; ----------------------------------------- 795 ; function spi1MasterInit 796 ; ----------------------------------------- 0000 797 _spi1MasterInit: 0002 798 ar2 = 0x02 0003 799 ar3 = 0x03 0004 800 ar4 = 0x04 0005 801 ar5 = 0x05 0006 802 ar6 = 0x06 0007 803 ar7 = 0x07 0000 804 ar0 = 0x00 0001 805 ar1 = 0x01 0000 806 C$spi1_master.c$93$1$1 ==. 807 ; libraries/src/spi_master/spi1_master.c:93: P2SEL |= 0x40; // USART1 takes priority over USART0 on Port 1. 0000 43 F5 40 808 orl _P2SEL,#0x40 0003 809 C$spi1_master.c$94$1$1 ==. 810 ; libraries/src/spi_master/spi1_master.c:94: PERCFG |= 0x02; // PERCFG.U1CFG (1) = 1 (Alt. 2) : USART1 uses alt. location 2. 0003 43 F1 02 811 orl _PERCFG,#0x02 0006 812 C$spi1_master.c$104$1$1 ==. 813 ; libraries/src/spi_master/spi1_master.c:104: P1SEL |= ((1<<5) | (1<<6)); // P1SEL.SELP1_5 = 1, P1SEL.SELP1_6 = 1 0006 43 F4 60 814 orl _P1SEL,#0x60 0009 815 C$spi1_master.c$111$1$1 ==. 816 ; libraries/src/spi_master/spi1_master.c:111: IP0 |= (1< 3000000) 001B C3 848 clr c 001C EA 849 mov a,r2 001D 94 17 850 subb a,#0x17 001F EB 851 mov a,r3 0020 94 00 852 subb a,#0x00 0022 EC 853 mov a,r4 0023 94 00 854 subb a,#0x00 0025 ED 855 mov a,r5 0026 94 00 856 subb a,#0x00 0028 40 0D 857 jc 00101$ 002A 74 C0 858 mov a,#0xC0 002C 9A 859 subb a,r2 002D 74 C6 860 mov a,#0xC6 002F 9B 861 subb a,r3 0030 74 2D 862 mov a,#0x2D 0032 9C 863 subb a,r4 0033 E4 864 clr a 0034 9D 865 subb a,r5 0035 50 01 866 jnc 00114$ 0037 867 00101$: 0037 868 C$spi1_master.c$125$1$1 ==. 869 ; libraries/src/spi_master/spi1_master.c:125: return; 0037 22 870 ret 0038 871 C$spi1_master.c$128$1$1 ==. 872 ; libraries/src/spi_master/spi1_master.c:128: while (freq > 495782) 0038 873 00114$: 0038 7E 00 874 mov r6,#0x00 003A 875 00104$: 003A C3 876 clr c 003B 74 A6 877 mov a,#0xA6 003D 9A 878 subb a,r2 003E 74 90 879 mov a,#0x90 0040 9B 880 subb a,r3 0041 74 07 881 mov a,#0x07 0043 9C 882 subb a,r4 0044 E4 883 clr a 0045 9D 884 subb a,r5 0046 50 10 885 jnc 00106$ 0048 886 C$spi1_master.c$130$2$2 ==. 887 ; libraries/src/spi_master/spi1_master.c:130: baudE++; 0048 0E 888 inc r6 0049 889 C$spi1_master.c$131$2$2 ==. 890 ; libraries/src/spi_master/spi1_master.c:131: freq /= 2; 0049 ED 891 mov a,r5 004A C3 892 clr c 004B 13 893 rrc a 004C FD 894 mov r5,a 004D EC 895 mov a,r4 004E 13 896 rrc a 004F FC 897 mov r4,a 0050 EB 898 mov a,r3 0051 13 899 rrc a 0052 FB 900 mov r3,a 0053 EA 901 mov a,r2 0054 13 902 rrc a 0055 FA 903 mov r2,a 0056 80 E2 904 sjmp 00104$ 0058 905 00106$: 0058 906 C$spi1_master.c$136$1$1 ==. 907 ; libraries/src/spi_master/spi1_master.c:136: baudMPlus256 = (freq * 11) + (freq * 8663 / 46875); 0058 78r00 908 mov r0,#__mullong_PARM_2 005A EA 909 mov a,r2 005B F2 910 movx @r0,a 005C 08 911 inc r0 005D EB 912 mov a,r3 005E F2 913 movx @r0,a 005F 08 914 inc r0 0060 EC 915 mov a,r4 0061 F2 916 movx @r0,a 0062 08 917 inc r0 0063 ED 918 mov a,r5 0064 F2 919 movx @r0,a 0065 90 00 0B 920 mov dptr,#(0x0B&0x00ff) 0068 E4 921 clr a 0069 F5 F0 922 mov b,a 006B C0 02 923 push ar2 006D C0 03 924 push ar3 006F C0 04 925 push ar4 0071 C0 05 926 push ar5 0073 C0 06 927 push ar6 0075 12s00r00 928 lcall __mullong 0078 85 82*06 929 mov _spi1MasterSetFrequency_sloc0_1_0,dpl 007B 85 83*07 930 mov (_spi1MasterSetFrequency_sloc0_1_0 + 1),dph 007E 85 F0*08 931 mov (_spi1MasterSetFrequency_sloc0_1_0 + 2),b 0081 F5*09 932 mov (_spi1MasterSetFrequency_sloc0_1_0 + 3),a 0083 D0 06 933 pop ar6 0085 D0 05 934 pop ar5 0087 D0 04 935 pop ar4 0089 D0 03 936 pop ar3 008B D0 02 937 pop ar2 008D 78r00 938 mov r0,#__mullong_PARM_2 008F EA 939 mov a,r2 0090 F2 940 movx @r0,a 0091 08 941 inc r0 0092 EB 942 mov a,r3 0093 F2 943 movx @r0,a 0094 08 944 inc r0 0095 EC 945 mov a,r4 0096 F2 946 movx @r0,a 0097 08 947 inc r0 0098 ED 948 mov a,r5 0099 F2 949 movx @r0,a 009A 90 21 D7 950 mov dptr,#0x21D7 009D E4 951 clr a 009E F5 F0 952 mov b,a 00A0 C0 06 953 push ar6 00A2 12s00r00 954 lcall __mullong 00A5 AC 82 955 mov r4,dpl 00A7 AD 83 956 mov r5,dph 00A9 AA F0 957 mov r2,b 00AB FB 958 mov r3,a 00AC 78r00 959 mov r0,#__divulong_PARM_2 00AE 74 1B 960 mov a,#0x1B 00B0 F2 961 movx @r0,a 00B1 08 962 inc r0 00B2 74 B7 963 mov a,#0xB7 00B4 F2 964 movx @r0,a 00B5 08 965 inc r0 00B6 E4 966 clr a 00B7 F2 967 movx @r0,a 00B8 08 968 inc r0 00B9 F2 969 movx @r0,a 00BA 8C 82 970 mov dpl,r4 00BC 8D 83 971 mov dph,r5 00BE 8A F0 972 mov b,r2 00C0 EB 973 mov a,r3 00C1 12s00r00 974 lcall __divulong 00C4 AA 82 975 mov r2,dpl 00C6 AB 83 976 mov r3,dph 00C8 AC F0 977 mov r4,b 00CA FD 978 mov r5,a 00CB D0 06 979 pop ar6 00CD EA 980 mov a,r2 00CE 25*06 981 add a,_spi1MasterSetFrequency_sloc0_1_0 00D0 FA 982 mov r2,a 00D1 EB 983 mov a,r3 00D2 35*07 984 addc a,(_spi1MasterSetFrequency_sloc0_1_0 + 1) 00D4 FB 985 mov r3,a 00D5 EC 986 mov a,r4 00D6 35*08 987 addc a,(_spi1MasterSetFrequency_sloc0_1_0 + 2) 00D8 FC 988 mov r4,a 00D9 ED 989 mov a,r5 00DA 35*09 990 addc a,(_spi1MasterSetFrequency_sloc0_1_0 + 3) 00DC FD 991 mov r5,a 00DD 992 C$spi1_master.c$139$1$1 ==. 993 ; libraries/src/spi_master/spi1_master.c:139: while (baudMPlus256 > 0x1ff) 00DD 994 00107$: 00DD C3 995 clr c 00DE 74 FF 996 mov a,#0xFF 00E0 9A 997 subb a,r2 00E1 74 01 998 mov a,#0x01 00E3 9B 999 subb a,r3 00E4 E4 1000 clr a 00E5 9C 1001 subb a,r4 00E6 E4 1002 clr a 00E7 9D 1003 subb a,r5 00E8 50 10 1004 jnc 00109$ 00EA 1005 C$spi1_master.c$141$2$3 ==. 1006 ; libraries/src/spi_master/spi1_master.c:141: baudE++; 00EA 0E 1007 inc r6 00EB 1008 C$spi1_master.c$142$2$3 ==. 1009 ; libraries/src/spi_master/spi1_master.c:142: baudMPlus256 /= 2; 00EB ED 1010 mov a,r5 00EC C3 1011 clr c 00ED 13 1012 rrc a 00EE FD 1013 mov r5,a 00EF EC 1014 mov a,r4 00F0 13 1015 rrc a 00F1 FC 1016 mov r4,a 00F2 EB 1017 mov a,r3 00F3 13 1018 rrc a 00F4 FB 1019 mov r3,a 00F5 EA 1020 mov a,r2 00F6 13 1021 rrc a 00F7 FA 1022 mov r2,a 00F8 80 E3 1023 sjmp 00107$ 00FA 1024 00109$: 00FA 1025 C$spi1_master.c$144$1$1 ==. 1026 ; libraries/src/spi_master/spi1_master.c:144: UNGCR &= 0xE0; // preserve CPOL, CPHA, ORDER (7:5) 00FA 53 FC E0 1027 anl _U1GCR,#0xE0 00FD 1028 C$spi1_master.c$145$1$1 ==. 1029 ; libraries/src/spi_master/spi1_master.c:145: UNGCR |= baudE; // UNGCR.BAUD_E (4:0) 00FD EE 1030 mov a,r6 00FE 42 FC 1031 orl _U1GCR,a 0100 1032 C$spi1_master.c$146$1$1 ==. 1033 ; libraries/src/spi_master/spi1_master.c:146: UNBAUD = baudMPlus256; // UNBAUD.BAUD_M (7:0) - only the lowest 8 bits of baudMPlus256 are used, so this is effectively baudMPlus256 - 256 0100 8A FA 1034 mov _U1BAUD,r2 0102 1035 C$spi1_master.c$147$1$1 ==. 0102 1036 XG$spi1MasterSetFrequency$0$0 ==. 0102 22 1037 ret 1038 ;------------------------------------------------------------ 1039 ;Allocation info for local variables in function 'spi1MasterSetClockPolarity' 1040 ;------------------------------------------------------------ 1041 ;------------------------------------------------------------ 0103 1042 G$spi1MasterSetClockPolarity$0$0 ==. 0103 1043 C$spi1_master.c$149$1$1 ==. 1044 ; libraries/src/spi_master/spi1_master.c:149: void spiNMasterSetClockPolarity(BIT polarity) 1045 ; ----------------------------------------- 1046 ; function spi1MasterSetClockPolarity 1047 ; ----------------------------------------- 0103 1048 _spi1MasterSetClockPolarity: 0103 1049 C$spi1_master.c$151$1$1 ==. 1050 ; libraries/src/spi_master/spi1_master.c:151: if (polarity == SPI_POLARITY_IDLE_LOW) 0103 20*00 04 1051 jb _spi1MasterSetClockPolarity_PARM_1,00102$ 0106 1052 C$spi1_master.c$153$2$2 ==. 1053 ; libraries/src/spi_master/spi1_master.c:153: UNGCR &= ~(1<<7); // SCK idle low (negative polarity) 0106 53 FC 7F 1054 anl _U1GCR,#0x7F 0109 22 1055 ret 010A 1056 00102$: 010A 1057 C$spi1_master.c$157$2$3 ==. 1058 ; libraries/src/spi_master/spi1_master.c:157: UNGCR |= (1<<7); // SCK idle high (positive polarity) 010A 43 FC 80 1059 orl _U1GCR,#0x80 010D 1060 C$spi1_master.c$159$1$1 ==. 010D 1061 XG$spi1MasterSetClockPolarity$0$0 ==. 010D 22 1062 ret 1063 ;------------------------------------------------------------ 1064 ;Allocation info for local variables in function 'spi1MasterSetClockPhase' 1065 ;------------------------------------------------------------ 1066 ;------------------------------------------------------------ 010E 1067 G$spi1MasterSetClockPhase$0$0 ==. 010E 1068 C$spi1_master.c$161$1$1 ==. 1069 ; libraries/src/spi_master/spi1_master.c:161: void spiNMasterSetClockPhase(BIT phase) 1070 ; ----------------------------------------- 1071 ; function spi1MasterSetClockPhase 1072 ; ----------------------------------------- 010E 1073 _spi1MasterSetClockPhase: 010E 1074 C$spi1_master.c$163$1$1 ==. 1075 ; libraries/src/spi_master/spi1_master.c:163: if (phase == SPI_PHASE_EDGE_LEADING) 010E 20*01 04 1076 jb _spi1MasterSetClockPhase_PARM_1,00102$ 0111 1077 C$spi1_master.c$165$2$2 ==. 1078 ; libraries/src/spi_master/spi1_master.c:165: UNGCR &= ~(1<<6); // data centered on leading (first) edge - rising for idle low, falling for idle high 0111 53 FC BF 1079 anl _U1GCR,#0xBF 0114 22 1080 ret 0115 1081 00102$: 0115 1082 C$spi1_master.c$169$2$3 ==. 1083 ; libraries/src/spi_master/spi1_master.c:169: UNGCR |= (1<<6); // data centered on trailing (second) edge - falling for idle low, rising for idle high 0115 43 FC 40 1084 orl _U1GCR,#0x40 0118 1085 C$spi1_master.c$171$1$1 ==. 0118 1086 XG$spi1MasterSetClockPhase$0$0 ==. 0118 22 1087 ret 1088 ;------------------------------------------------------------ 1089 ;Allocation info for local variables in function 'spi1MasterSetBitOrder' 1090 ;------------------------------------------------------------ 1091 ;------------------------------------------------------------ 0119 1092 G$spi1MasterSetBitOrder$0$0 ==. 0119 1093 C$spi1_master.c$173$1$1 ==. 1094 ; libraries/src/spi_master/spi1_master.c:173: void spiNMasterSetBitOrder(BIT bitOrder) 1095 ; ----------------------------------------- 1096 ; function spi1MasterSetBitOrder 1097 ; ----------------------------------------- 0119 1098 _spi1MasterSetBitOrder: 0119 1099 C$spi1_master.c$175$1$1 ==. 1100 ; libraries/src/spi_master/spi1_master.c:175: if (bitOrder == SPI_BIT_ORDER_LSB_FIRST) 0119 30*02 04 1101 jnb _spi1MasterSetBitOrder_PARM_1,00102$ 011C 1102 C$spi1_master.c$177$2$2 ==. 1103 ; libraries/src/spi_master/spi1_master.c:177: UNGCR &= ~(1<<5); // LSB first 011C 53 FC DF 1104 anl _U1GCR,#0xDF 011F 22 1105 ret 0120 1106 00102$: 0120 1107 C$spi1_master.c$181$2$3 ==. 1108 ; libraries/src/spi_master/spi1_master.c:181: UNGCR |= (1<<5); // MSB first 0120 43 FC 20 1109 orl _U1GCR,#0x20 0123 1110 C$spi1_master.c$183$1$1 ==. 0123 1111 XG$spi1MasterSetBitOrder$0$0 ==. 0123 22 1112 ret 1113 ;------------------------------------------------------------ 1114 ;Allocation info for local variables in function 'spi1MasterBusy' 1115 ;------------------------------------------------------------ 1116 ;------------------------------------------------------------ 0124 1117 G$spi1MasterBusy$0$0 ==. 0124 1118 C$spi1_master.c$185$1$1 ==. 1119 ; libraries/src/spi_master/spi1_master.c:185: BIT spiNMasterBusy(void) 1120 ; ----------------------------------------- 1121 ; function spi1MasterBusy 1122 ; ----------------------------------------- 0124 1123 _spi1MasterBusy: 0124 1124 C$spi1_master.c$187$1$1 ==. 1125 ; libraries/src/spi_master/spi1_master.c:187: return URXNIE; 0124 A2 AB 1126 mov c,_URX1IE 0126 1127 C$spi1_master.c$188$1$1 ==. 0126 1128 XG$spi1MasterBusy$0$0 ==. 0126 22 1129 ret 1130 ;------------------------------------------------------------ 1131 ;Allocation info for local variables in function 'spi1MasterBytesLeft' 1132 ;------------------------------------------------------------ 1133 ;------------------------------------------------------------ 0127 1134 G$spi1MasterBytesLeft$0$0 ==. 0127 1135 C$spi1_master.c$190$1$1 ==. 1136 ; libraries/src/spi_master/spi1_master.c:190: uint16 spiNMasterBytesLeft(void) 1137 ; ----------------------------------------- 1138 ; function spi1MasterBytesLeft 1139 ; ----------------------------------------- 0127 1140 _spi1MasterBytesLeft: 0127 1141 C$spi1_master.c$195$1$1 ==. 1142 ; libraries/src/spi_master/spi1_master.c:195: URXNIE = 0; 0127 C2 AB 1143 clr _URX1IE 0129 1144 C$spi1_master.c$196$1$1 ==. 1145 ; libraries/src/spi_master/spi1_master.c:196: bytes = bytesLeft; 0129 AA*04 1146 mov r2,_bytesLeft 012B AB*05 1147 mov r3,(_bytesLeft + 1) 012D 1148 C$spi1_master.c$197$1$1 ==. 1149 ; libraries/src/spi_master/spi1_master.c:197: if (bytes) URXNIE = 1; 012D EA 1150 mov a,r2 012E 4B 1151 orl a,r3 012F 60 02 1152 jz 00102$ 0131 D2 AB 1153 setb _URX1IE 0133 1154 00102$: 0133 1155 C$spi1_master.c$199$1$1 ==. 1156 ; libraries/src/spi_master/spi1_master.c:199: return bytes; 0133 8A 82 1157 mov dpl,r2 0135 8B 83 1158 mov dph,r3 0137 1159 C$spi1_master.c$200$1$1 ==. 0137 1160 XG$spi1MasterBytesLeft$0$0 ==. 0137 22 1161 ret 1162 ;------------------------------------------------------------ 1163 ;Allocation info for local variables in function 'spi1MasterTransfer' 1164 ;------------------------------------------------------------ 1165 ;------------------------------------------------------------ 0138 1166 G$spi1MasterTransfer$0$0 ==. 0138 1167 C$spi1_master.c$202$1$1 ==. 1168 ; libraries/src/spi_master/spi1_master.c:202: void spiNMasterTransfer(const uint8 XDATA * txBuffer, uint8 XDATA * rxBuffer, uint16 size) 1169 ; ----------------------------------------- 1170 ; function spi1MasterTransfer 1171 ; ----------------------------------------- 0138 1172 _spi1MasterTransfer: 0138 AA 82 1173 mov r2,dpl 013A AB 83 1174 mov r3,dph 013C 1175 C$spi1_master.c$204$1$1 ==. 1176 ; libraries/src/spi_master/spi1_master.c:204: if (size) 013C 78r02 1177 mov r0,#_spi1MasterTransfer_PARM_3 013E E2 1178 movx a,@r0 013F F5 F0 1179 mov b,a 0141 08 1180 inc r0 0142 E2 1181 movx a,@r0 0143 45 F0 1182 orl a,b 0145 60 1F 1183 jz 00103$ 0147 1184 C$spi1_master.c$206$2$2 ==. 1185 ; libraries/src/spi_master/spi1_master.c:206: txPointer = txBuffer; 0147 8A*00 1186 mov _txPointer,r2 0149 8B*01 1187 mov (_txPointer + 1),r3 014B 1188 C$spi1_master.c$207$2$2 ==. 1189 ; libraries/src/spi_master/spi1_master.c:207: rxPointer = rxBuffer; 014B 78r00 1190 mov r0,#_spi1MasterTransfer_PARM_2 014D E2 1191 movx a,@r0 014E F5*02 1192 mov _rxPointer,a 0150 08 1193 inc r0 0151 E2 1194 movx a,@r0 0152 F5*03 1195 mov (_rxPointer + 1),a 0154 1196 C$spi1_master.c$208$2$2 ==. 1197 ; libraries/src/spi_master/spi1_master.c:208: bytesLeft = size; 0154 78r02 1198 mov r0,#_spi1MasterTransfer_PARM_3 0156 E2 1199 movx a,@r0 0157 F5*04 1200 mov _bytesLeft,a 0159 08 1201 inc r0 015A E2 1202 movx a,@r0 015B F5*05 1203 mov (_bytesLeft + 1),a 015D 1204 C$spi1_master.c$210$2$2 ==. 1205 ; libraries/src/spi_master/spi1_master.c:210: UNDBUF = *txBuffer; // transmit first byte 015D 8A 82 1206 mov dpl,r2 015F 8B 83 1207 mov dph,r3 0161 E0 1208 movx a,@dptr 0162 F5 F9 1209 mov _U1DBUF,a 0164 1210 C$spi1_master.c$211$2$2 ==. 1211 ; libraries/src/spi_master/spi1_master.c:211: URXNIE = 1; // Enable RX interrupt. 0164 D2 AB 1212 setb _URX1IE 0166 1213 00103$: 0166 1214 C$spi1_master.c$213$2$1 ==. 0166 1215 XG$spi1MasterTransfer$0$0 ==. 0166 22 1216 ret 1217 ;------------------------------------------------------------ 1218 ;Allocation info for local variables in function 'spi1MasterSendByte' 1219 ;------------------------------------------------------------ 1220 ;byte Allocated with name '_spi1MasterSendByte_byte_1_1' 1221 ;rxByte Allocated with name '_spi1MasterSendByte_rxByte_1_1' 1222 ;------------------------------------------------------------ 0167 1223 G$spi1MasterSendByte$0$0 ==. 0167 1224 C$spi1_master.c$215$2$1 ==. 1225 ; libraries/src/spi_master/spi1_master.c:215: uint8 spiNMasterSendByte(uint8 XDATA byte) 1226 ; ----------------------------------------- 1227 ; function spi1MasterSendByte 1228 ; ----------------------------------------- 0167 1229 _spi1MasterSendByte: 0167 E5 82 1230 mov a,dpl 0169 90s00r00 1231 mov dptr,#_spi1MasterSendByte_byte_1_1 016C F0 1232 movx @dptr,a 016D 1233 C$spi1_master.c$219$1$1 ==. 1234 ; libraries/src/spi_master/spi1_master.c:219: rxPointer = &rxByte; 016D 75*02r01 1235 mov _rxPointer,#_spi1MasterSendByte_rxByte_1_1 0170 75*03s00 1236 mov (_rxPointer + 1),#(_spi1MasterSendByte_rxByte_1_1 >> 8) 0173 1237 C$spi1_master.c$220$1$1 ==. 1238 ; libraries/src/spi_master/spi1_master.c:220: bytesLeft = 1; 0173 75*04 01 1239 mov _bytesLeft,#0x01 0176 75*05 00 1240 mov (_bytesLeft + 1),#0x00 0179 1241 C$spi1_master.c$222$1$1 ==. 1242 ; libraries/src/spi_master/spi1_master.c:222: UNDBUF = byte; 0179 90s00r00 1243 mov dptr,#_spi1MasterSendByte_byte_1_1 017C E0 1244 movx a,@dptr 017D F5 F9 1245 mov _U1DBUF,a 017F 1246 C$spi1_master.c$223$1$1 ==. 1247 ; libraries/src/spi_master/spi1_master.c:223: URXNIE = 1; // Enable RX interrupt. 017F D2 AB 1248 setb _URX1IE 0181 1249 C$spi1_master.c$225$1$1 ==. 1250 ; libraries/src/spi_master/spi1_master.c:225: while (bytesLeft); 0181 1251 00101$: 0181 E5*04 1252 mov a,_bytesLeft 0183 45*05 1253 orl a,(_bytesLeft + 1) 0185 70 FA 1254 jnz 00101$ 0187 1255 C$spi1_master.c$226$1$1 ==. 1256 ; libraries/src/spi_master/spi1_master.c:226: return rxByte; 0187 90s00r01 1257 mov dptr,#_spi1MasterSendByte_rxByte_1_1 018A E0 1258 movx a,@dptr 018B 1259 C$spi1_master.c$227$1$1 ==. 018B 1260 XG$spi1MasterSendByte$0$0 ==. 018B F5 82 1261 mov dpl,a 018D 22 1262 ret 1263 ;------------------------------------------------------------ 1264 ;Allocation info for local variables in function 'spi1MasterReceiveByte' 1265 ;------------------------------------------------------------ 1266 ;------------------------------------------------------------ 018E 1267 G$spi1MasterReceiveByte$0$0 ==. 018E 1268 C$spi1_master.c$229$1$1 ==. 1269 ; libraries/src/spi_master/spi1_master.c:229: uint8 spiNMasterReceiveByte(void) 1270 ; ----------------------------------------- 1271 ; function spi1MasterReceiveByte 1272 ; ----------------------------------------- 018E 1273 _spi1MasterReceiveByte: 018E 1274 C$spi1_master.c$231$1$1 ==. 1275 ; libraries/src/spi_master/spi1_master.c:231: return spiNMasterSendByte(0xFF); 018E 75 82 FF 1276 mov dpl,#0xFF 0191 1277 C$spi1_master.c$232$1$1 ==. 0191 1278 XG$spi1MasterReceiveByte$0$0 ==. 0191 02s01r67 1279 ljmp _spi1MasterSendByte 1280 ;------------------------------------------------------------ 1281 ;Allocation info for local variables in function 'ISR_URX1' 1282 ;------------------------------------------------------------ 1283 ;------------------------------------------------------------ 0194 1284 G$ISR_URX1$0$0 ==. 0194 1285 C$spi1_master.c$234$1$1 ==. 1286 ; libraries/src/spi_master/spi1_master.c:234: ISR_URX() 1287 ; ----------------------------------------- 1288 ; function ISR_URX1 1289 ; ----------------------------------------- 0194 1290 _ISR_URX1: 0194 C0 E0 1291 push acc 0196 C0 82 1292 push dpl 0198 C0 83 1293 push dph 019A C0 D0 1294 push psw 019C 75 D0 00 1295 mov psw,#0x00 019F 1296 C$spi1_master.c$236$1$1 ==. 1297 ; libraries/src/spi_master/spi1_master.c:236: URXNIF = 0; 019F C2 8F 1298 clr _URX1IF 01A1 1299 C$spi1_master.c$238$1$1 ==. 1300 ; libraries/src/spi_master/spi1_master.c:238: *rxPointer = UNDBUF; 01A1 85*02 82 1301 mov dpl,_rxPointer 01A4 85*03 83 1302 mov dph,(_rxPointer + 1) 01A7 E5 F9 1303 mov a,_U1DBUF 01A9 F0 1304 movx @dptr,a 01AA 1305 C$spi1_master.c$239$1$1 ==. 1306 ; libraries/src/spi_master/spi1_master.c:239: rxPointer++; 01AA 05*02 1307 inc _rxPointer 01AC E4 1308 clr a 01AD B5*02 02 1309 cjne a,_rxPointer,00107$ 01B0 05*03 1310 inc (_rxPointer + 1) 01B2 1311 00107$: 01B2 1312 C$spi1_master.c$240$1$1 ==. 1313 ; libraries/src/spi_master/spi1_master.c:240: bytesLeft--; 01B2 15*04 1314 dec _bytesLeft 01B4 74 FF 1315 mov a,#0xff 01B6 B5*04 02 1316 cjne a,_bytesLeft,00108$ 01B9 15*05 1317 dec (_bytesLeft + 1) 01BB 1318 00108$: 01BB 1319 C$spi1_master.c$242$1$1 ==. 1320 ; libraries/src/spi_master/spi1_master.c:242: if (bytesLeft) 01BB E5*04 1321 mov a,_bytesLeft 01BD 45*05 1322 orl a,(_bytesLeft + 1) 01BF 60 13 1323 jz 00102$ 01C1 1324 C$spi1_master.c$244$2$2 ==. 1325 ; libraries/src/spi_master/spi1_master.c:244: txPointer++; 01C1 05*00 1326 inc _txPointer 01C3 E4 1327 clr a 01C4 B5*00 02 1328 cjne a,_txPointer,00110$ 01C7 05*01 1329 inc (_txPointer + 1) 01C9 1330 00110$: 01C9 1331 C$spi1_master.c$245$2$2 ==. 1332 ; libraries/src/spi_master/spi1_master.c:245: UNDBUF = *txPointer; 01C9 85*00 82 1333 mov dpl,_txPointer 01CC 85*01 83 1334 mov dph,(_txPointer + 1) 01CF E0 1335 movx a,@dptr 01D0 F5 F9 1336 mov _U1DBUF,a 01D2 80 02 1337 sjmp 00104$ 01D4 1338 00102$: 01D4 1339 C$spi1_master.c$249$2$3 ==. 1340 ; libraries/src/spi_master/spi1_master.c:249: URXNIE = 0; 01D4 C2 AB 1341 clr _URX1IE 01D6 1342 00104$: 01D6 D0 D0 1343 pop psw 01D8 D0 83 1344 pop dph 01DA D0 82 1345 pop dpl 01DC D0 E0 1346 pop acc 01DE 1347 C$spi1_master.c$251$1$1 ==. 01DE 1348 XG$ISR_URX1$0$0 ==. 01DE 32 1349 reti 1350 ; eliminated unneeded push/pop b 1351 .area CSEG (CODE) 1352 .area CONST (CODE) 1353 .area XINIT (CODE) 1354 .area CABS (ABS,CODE)