M:spi1_master
F:G$spi1MasterInit$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$spi1MasterSetFrequency$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$spi1MasterSetClockPolarity$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$spi1MasterSetClockPhase$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$spi1MasterSetBitOrder$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$spi1MasterBusy$0$0({2}DF,SB0$1:U),Z,0,0,0,0,0
F:G$spi1MasterBytesLeft$0$0({2}DF,SI:U),Z,0,0,0,0,0
F:G$spi1MasterTransfer$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$spi1MasterSendByte$0$0({2}DF,SC:U),Z,0,0,0,0,0
F:G$spi1MasterReceiveByte$0$0({2}DF,SC:U),Z,0,0,0,0,0
F:G$ISR_URX1$0$0({2}DF,SV:S),Z,0,0,1,3,0
T:Fspi1_master$__00010000[({0}S:S$SRCADDRH$0$0({1}SC:U),Z,0,0)({1}S:S$SRCADDRL$0$0({1}SC:U),Z,0,0)({2}S:S$DESTADDRH$0$0({1}SC:U),Z,0,0)({3}S:S$DESTADDRL$0$0({1}SC:U),Z,0,0)({4}S:S$VLEN_LENH$0$0({1}SC:U),Z,0,0)({5}S:S$LENL$0$0({1}SC:U),Z,0,0)({6}S:S$DC6$0$0({1}SC:U),Z,0,0)({7}S:S$DC7$0$0({1}SC:U),Z,0,0)]
F:G$ISR_URX1$0$0({2}DF,SV:S),Z,0,0,1,3,0
F:G$ISR_URX1$0$0({2}DF,SV:S),Z,0,0,1,3,0
F:G$ISR_URX1$0$0({2}DF,SV:S),Z,0,0,1,3,0
S:Fspi1_master$txPointer$0$0({2}DX,SC:U),E,0,0
S:Fspi1_master$rxPointer$0$0({2}DX,SC:U),E,0,0
S:Fspi1_master$bytesLeft$0$0({2}SI:U),E,0,0
S:Lspi1MasterSetFrequency$sloc0$1$0({4}SL:U),E,0,0
S:Lspi1MasterSetClockPolarity$polarity$1$1({1}SB0$1:U),H,0,0
S:Lspi1MasterSetClockPhase$phase$1$1({1}SB0$1:U),H,0,0
S:Lspi1MasterSetBitOrder$bitOrder$1$1({1}SB0$1:U),H,0,0
S:Lspi1MasterSetFrequency$freq$1$1({4}SL:U),R,0,0,[r2,r3,r4,r5]
S:Lspi1MasterSetFrequency$baudMPlus256$1$1({4}SL:U),R,0,0,[r2,r3,r4,r5]
S:Lspi1MasterSetFrequency$baudE$1$1({1}SC:U),R,0,0,[r6]
S:Lspi1MasterBytesLeft$bytes$1$1({2}SI:U),R,0,0,[r2,r3]
S:Lspi1MasterTransfer$rxBuffer$1$1({2}DX,SC:U),P,0,0
S:Lspi1MasterTransfer$size$1$1({2}SI:U),P,0,0
S:Lspi1MasterTransfer$txBuffer$1$1({2}DX,SC:U),R,0,0,[r2,r3]
S:Fspi1_master$SYNC1$0$0({1}SC:U),F,0,0
S:Fspi1_master$SYNC0$0$0({1}SC:U),F,0,0
S:Fspi1_master$PKTLEN$0$0({1}SC:U),F,0,0
S:Fspi1_master$PKTCTRL1$0$0({1}SC:U),F,0,0
S:Fspi1_master$PKTCTRL0$0$0({1}SC:U),F,0,0
S:Fspi1_master$ADDR$0$0({1}SC:U),F,0,0
S:Fspi1_master$CHANNR$0$0({1}SC:U),F,0,0
S:Fspi1_master$FSCTRL1$0$0({1}SC:U),F,0,0
S:Fspi1_master$FSCTRL0$0$0({1}SC:U),F,0,0
S:Fspi1_master$FREQ2$0$0({1}SC:U),F,0,0
S:Fspi1_master$FREQ1$0$0({1}SC:U),F,0,0
S:Fspi1_master$FREQ0$0$0({1}SC:U),F,0,0
S:Fspi1_master$MDMCFG4$0$0({1}SC:U),F,0,0
S:Fspi1_master$MDMCFG3$0$0({1}SC:U),F,0,0
S:Fspi1_master$MDMCFG2$0$0({1}SC:U),F,0,0
S:Fspi1_master$MDMCFG1$0$0({1}SC:U),F,0,0
S:Fspi1_master$MDMCFG0$0$0({1}SC:U),F,0,0
S:Fspi1_master$DEVIATN$0$0({1}SC:U),F,0,0
S:Fspi1_master$MCSM2$0$0({1}SC:U),F,0,0
S:Fspi1_master$MCSM1$0$0({1}SC:U),F,0,0
S:Fspi1_master$MCSM0$0$0({1}SC:U),F,0,0
S:Fspi1_master$FOCCFG$0$0({1}SC:U),F,0,0
S:Fspi1_master$BSCFG$0$0({1}SC:U),F,0,0
S:Fspi1_master$AGCCTRL2$0$0({1}SC:U),F,0,0
S:Fspi1_master$AGCCTRL1$0$0({1}SC:U),F,0,0
S:Fspi1_master$AGCCTRL0$0$0({1}SC:U),F,0,0
S:Fspi1_master$FREND1$0$0({1}SC:U),F,0,0
S:Fspi1_master$FREND0$0$0({1}SC:U),F,0,0
S:Fspi1_master$FSCAL3$0$0({1}SC:U),F,0,0
S:Fspi1_master$FSCAL2$0$0({1}SC:U),F,0,0
S:Fspi1_master$FSCAL1$0$0({1}SC:U),F,0,0
S:Fspi1_master$FSCAL0$0$0({1}SC:U),F,0,0
S:Fspi1_master$TEST2$0$0({1}SC:U),F,0,0
S:Fspi1_master$TEST1$0$0({1}SC:U),F,0,0
S:Fspi1_master$TEST0$0$0({1}SC:U),F,0,0
S:Fspi1_master$PA_TABLE0$0$0({1}SC:U),F,0,0
S:Fspi1_master$IOCFG2$0$0({1}SC:U),F,0,0
S:Fspi1_master$IOCFG1$0$0({1}SC:U),F,0,0
S:Fspi1_master$IOCFG0$0$0({1}SC:U),F,0,0
S:Fspi1_master$PARTNUM$0$0({1}SC:U),F,0,0
S:Fspi1_master$VERSION$0$0({1}SC:U),F,0,0
S:Fspi1_master$FREQEST$0$0({1}SC:U),F,0,0
S:Fspi1_master$LQI$0$0({1}SC:U),F,0,0
S:Fspi1_master$RSSI$0$0({1}SC:U),F,0,0
S:Fspi1_master$MARCSTATE$0$0({1}SC:U),F,0,0
S:Fspi1_master$PKTSTATUS$0$0({1}SC:U),F,0,0
S:Fspi1_master$VCO_VC_DAC$0$0({1}SC:U),F,0,0
S:Fspi1_master$I2SCFG0$0$0({1}SC:U),F,0,0
S:Fspi1_master$I2SCFG1$0$0({1}SC:U),F,0,0
S:Fspi1_master$I2SDATL$0$0({1}SC:U),F,0,0
S:Fspi1_master$I2SDATH$0$0({1}SC:U),F,0,0
S:Fspi1_master$I2SWCNT$0$0({1}SC:U),F,0,0
S:Fspi1_master$I2SSTAT$0$0({1}SC:U),F,0,0
S:Fspi1_master$I2SCLKF0$0$0({1}SC:U),F,0,0
S:Fspi1_master$I2SCLKF1$0$0({1}SC:U),F,0,0
S:Fspi1_master$I2SCLKF2$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBADDR$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBPOW$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBIIF$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBOIF$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBCIF$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBIIE$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBOIE$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBCIE$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBFRML$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBFRMH$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBINDEX$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBMAXI$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBCSIL$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBCSIH$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBMAXO$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBCSOL$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBCSOH$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBCNTL$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBCNTH$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBF0$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBF1$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBF2$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBF3$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBF4$0$0({1}SC:U),F,0,0
S:Fspi1_master$USBF5$0$0({1}SC:U),F,0,0
S:Lspi1MasterSendByte$byte$1$1({1}SC:U),F,0,0
S:Lspi1MasterSendByte$rxByte$1$1({1}SC:U),F,0,0
S:Fspi1_master$P0$0$0({1}SC:U),I,0,0
S:Fspi1_master$SP$0$0({1}SC:U),I,0,0
S:Fspi1_master$DPL0$0$0({1}SC:U),I,0,0
S:Fspi1_master$DPH0$0$0({1}SC:U),I,0,0
S:Fspi1_master$DPL1$0$0({1}SC:U),I,0,0
S:Fspi1_master$DPH1$0$0({1}SC:U),I,0,0
S:Fspi1_master$U0CSR$0$0({1}SC:U),I,0,0
S:Fspi1_master$PCON$0$0({1}SC:U),I,0,0
S:Fspi1_master$TCON$0$0({1}SC:U),I,0,0
S:Fspi1_master$P0IFG$0$0({1}SC:U),I,0,0
S:Fspi1_master$P1IFG$0$0({1}SC:U),I,0,0
S:Fspi1_master$P2IFG$0$0({1}SC:U),I,0,0
S:Fspi1_master$PICTL$0$0({1}SC:U),I,0,0
S:Fspi1_master$P1IEN$0$0({1}SC:U),I,0,0
S:Fspi1_master$P0INP$0$0({1}SC:U),I,0,0
S:Fspi1_master$P1$0$0({1}SC:U),I,0,0
S:Fspi1_master$RFIM$0$0({1}SC:U),I,0,0
S:Fspi1_master$DPS$0$0({1}SC:U),I,0,0
S:Fspi1_master$MPAGE$0$0({1}SC:U),I,0,0
S:Fspi1_master$ENDIAN$0$0({1}SC:U),I,0,0
S:Fspi1_master$S0CON$0$0({1}SC:U),I,0,0
S:Fspi1_master$IEN2$0$0({1}SC:U),I,0,0
S:Fspi1_master$S1CON$0$0({1}SC:U),I,0,0
S:Fspi1_master$T2CT$0$0({1}SC:U),I,0,0
S:Fspi1_master$T2PR$0$0({1}SC:U),I,0,0
S:Fspi1_master$T2CTL$0$0({1}SC:U),I,0,0
S:Fspi1_master$P2$0$0({1}SC:U),I,0,0
S:Fspi1_master$WORIRQ$0$0({1}SC:U),I,0,0
S:Fspi1_master$WORCTRL$0$0({1}SC:U),I,0,0
S:Fspi1_master$WOREVT0$0$0({1}SC:U),I,0,0
S:Fspi1_master$WOREVT1$0$0({1}SC:U),I,0,0
S:Fspi1_master$WORTIME0$0$0({1}SC:U),I,0,0
S:Fspi1_master$WORTIME1$0$0({1}SC:U),I,0,0
S:Fspi1_master$IEN0$0$0({1}SC:U),I,0,0
S:Fspi1_master$IP0$0$0({1}SC:U),I,0,0
S:Fspi1_master$FWT$0$0({1}SC:U),I,0,0
S:Fspi1_master$FADDRL$0$0({1}SC:U),I,0,0
S:Fspi1_master$FADDRH$0$0({1}SC:U),I,0,0
S:Fspi1_master$FCTL$0$0({1}SC:U),I,0,0
S:Fspi1_master$FWDATA$0$0({1}SC:U),I,0,0
S:Fspi1_master$ENCDI$0$0({1}SC:U),I,0,0
S:Fspi1_master$ENCDO$0$0({1}SC:U),I,0,0
S:Fspi1_master$ENCCS$0$0({1}SC:U),I,0,0
S:Fspi1_master$ADCCON1$0$0({1}SC:U),I,0,0
S:Fspi1_master$ADCCON2$0$0({1}SC:U),I,0,0
S:Fspi1_master$ADCCON3$0$0({1}SC:U),I,0,0
S:Fspi1_master$IEN1$0$0({1}SC:U),I,0,0
S:Fspi1_master$IP1$0$0({1}SC:U),I,0,0
S:Fspi1_master$ADCL$0$0({1}SC:U),I,0,0
S:Fspi1_master$ADCH$0$0({1}SC:U),I,0,0
S:Fspi1_master$RNDL$0$0({1}SC:U),I,0,0
S:Fspi1_master$RNDH$0$0({1}SC:U),I,0,0
S:Fspi1_master$SLEEP$0$0({1}SC:U),I,0,0
S:Fspi1_master$IRCON$0$0({1}SC:U),I,0,0
S:Fspi1_master$U0DBUF$0$0({1}SC:U),I,0,0
S:Fspi1_master$U0BAUD$0$0({1}SC:U),I,0,0
S:Fspi1_master$U0UCR$0$0({1}SC:U),I,0,0
S:Fspi1_master$U0GCR$0$0({1}SC:U),I,0,0
S:Fspi1_master$CLKCON$0$0({1}SC:U),I,0,0
S:Fspi1_master$MEMCTR$0$0({1}SC:U),I,0,0
S:Fspi1_master$WDCTL$0$0({1}SC:U),I,0,0
S:Fspi1_master$T3CNT$0$0({1}SC:U),I,0,0
S:Fspi1_master$T3CTL$0$0({1}SC:U),I,0,0
S:Fspi1_master$T3CCTL0$0$0({1}SC:U),I,0,0
S:Fspi1_master$T3CC0$0$0({1}SC:U),I,0,0
S:Fspi1_master$T3CCTL1$0$0({1}SC:U),I,0,0
S:Fspi1_master$T3CC1$0$0({1}SC:U),I,0,0
S:Fspi1_master$PSW$0$0({1}SC:U),I,0,0
S:Fspi1_master$DMAIRQ$0$0({1}SC:U),I,0,0
S:Fspi1_master$DMA1CFGL$0$0({1}SC:U),I,0,0
S:Fspi1_master$DMA1CFGH$0$0({1}SC:U),I,0,0
S:Fspi1_master$DMA0CFGL$0$0({1}SC:U),I,0,0
S:Fspi1_master$DMA0CFGH$0$0({1}SC:U),I,0,0
S:Fspi1_master$DMAARM$0$0({1}SC:U),I,0,0
S:Fspi1_master$DMAREQ$0$0({1}SC:U),I,0,0
S:Fspi1_master$TIMIF$0$0({1}SC:U),I,0,0
S:Fspi1_master$RFD$0$0({1}SC:U),I,0,0
S:Fspi1_master$T1CC0L$0$0({1}SC:U),I,0,0
S:Fspi1_master$T1CC0H$0$0({1}SC:U),I,0,0
S:Fspi1_master$T1CC1L$0$0({1}SC:U),I,0,0
S:Fspi1_master$T1CC1H$0$0({1}SC:U),I,0,0
S:Fspi1_master$T1CC2L$0$0({1}SC:U),I,0,0
S:Fspi1_master$T1CC2H$0$0({1}SC:U),I,0,0
S:Fspi1_master$ACC$0$0({1}SC:U),I,0,0
S:Fspi1_master$RFST$0$0({1}SC:U),I,0,0
S:Fspi1_master$T1CNTL$0$0({1}SC:U),I,0,0
S:Fspi1_master$T1CNTH$0$0({1}SC:U),I,0,0
S:Fspi1_master$T1CTL$0$0({1}SC:U),I,0,0
S:Fspi1_master$T1CCTL0$0$0({1}SC:U),I,0,0
S:Fspi1_master$T1CCTL1$0$0({1}SC:U),I,0,0
S:Fspi1_master$T1CCTL2$0$0({1}SC:U),I,0,0
S:Fspi1_master$IRCON2$0$0({1}SC:U),I,0,0
S:Fspi1_master$RFIF$0$0({1}SC:U),I,0,0
S:Fspi1_master$T4CNT$0$0({1}SC:U),I,0,0
S:Fspi1_master$T4CTL$0$0({1}SC:U),I,0,0
S:Fspi1_master$T4CCTL0$0$0({1}SC:U),I,0,0
S:Fspi1_master$T4CC0$0$0({1}SC:U),I,0,0
S:Fspi1_master$T4CCTL1$0$0({1}SC:U),I,0,0
S:Fspi1_master$T4CC1$0$0({1}SC:U),I,0,0
S:Fspi1_master$B$0$0({1}SC:U),I,0,0
S:Fspi1_master$PERCFG$0$0({1}SC:U),I,0,0
S:Fspi1_master$ADCCFG$0$0({1}SC:U),I,0,0
S:Fspi1_master$P0SEL$0$0({1}SC:U),I,0,0
S:Fspi1_master$P1SEL$0$0({1}SC:U),I,0,0
S:Fspi1_master$P2SEL$0$0({1}SC:U),I,0,0
S:Fspi1_master$P1INP$0$0({1}SC:U),I,0,0
S:Fspi1_master$P2INP$0$0({1}SC:U),I,0,0
S:Fspi1_master$U1CSR$0$0({1}SC:U),I,0,0
S:Fspi1_master$U1DBUF$0$0({1}SC:U),I,0,0
S:Fspi1_master$U1BAUD$0$0({1}SC:U),I,0,0
S:Fspi1_master$U1UCR$0$0({1}SC:U),I,0,0
S:Fspi1_master$U1GCR$0$0({1}SC:U),I,0,0
S:Fspi1_master$P0DIR$0$0({1}SC:U),I,0,0
S:Fspi1_master$P1DIR$0$0({1}SC:U),I,0,0
S:Fspi1_master$P2DIR$0$0({1}SC:U),I,0,0
S:Fspi1_master$DMA0CFG$0$0({2}SI:U),I,0,0
S:Fspi1_master$DMA1CFG$0$0({2}SI:U),I,0,0
S:Fspi1_master$FADDR$0$0({2}SI:U),I,0,0
S:Fspi1_master$ADC$0$0({2}SI:U),I,0,0
S:Fspi1_master$T1CC0$0$0({2}SI:U),I,0,0
S:Fspi1_master$T1CC1$0$0({2}SI:U),I,0,0
S:Fspi1_master$T1CC2$0$0({2}SI:U),I,0,0
S:Fspi1_master$P0_0$0$0({1}SX:U),J,0,0
S:Fspi1_master$P0_1$0$0({1}SX:U),J,0,0
S:Fspi1_master$P0_2$0$0({1}SX:U),J,0,0
S:Fspi1_master$P0_3$0$0({1}SX:U),J,0,0
S:Fspi1_master$P0_4$0$0({1}SX:U),J,0,0
S:Fspi1_master$P0_5$0$0({1}SX:U),J,0,0
S:Fspi1_master$P0_6$0$0({1}SX:U),J,0,0
S:Fspi1_master$P0_7$0$0({1}SX:U),J,0,0
S:Fspi1_master$_TCON_0$0$0({1}SX:U),J,0,0
S:Fspi1_master$RFTXRXIF$0$0({1}SX:U),J,0,0
S:Fspi1_master$_TCON_2$0$0({1}SX:U),J,0,0
S:Fspi1_master$URX0IF$0$0({1}SX:U),J,0,0
S:Fspi1_master$_TCON_4$0$0({1}SX:U),J,0,0
S:Fspi1_master$ADCIF$0$0({1}SX:U),J,0,0
S:Fspi1_master$_TCON_6$0$0({1}SX:U),J,0,0
S:Fspi1_master$URX1IF$0$0({1}SX:U),J,0,0
S:Fspi1_master$P1_0$0$0({1}SX:U),J,0,0
S:Fspi1_master$P1_1$0$0({1}SX:U),J,0,0
S:Fspi1_master$P1_2$0$0({1}SX:U),J,0,0
S:Fspi1_master$P1_3$0$0({1}SX:U),J,0,0
S:Fspi1_master$P1_4$0$0({1}SX:U),J,0,0
S:Fspi1_master$P1_5$0$0({1}SX:U),J,0,0
S:Fspi1_master$P1_6$0$0({1}SX:U),J,0,0
S:Fspi1_master$P1_7$0$0({1}SX:U),J,0,0
S:Fspi1_master$ENCIF_0$0$0({1}SX:U),J,0,0
S:Fspi1_master$ENCIF_1$0$0({1}SX:U),J,0,0
S:Fspi1_master$_SOCON2$0$0({1}SX:U),J,0,0
S:Fspi1_master$_SOCON3$0$0({1}SX:U),J,0,0
S:Fspi1_master$_SOCON4$0$0({1}SX:U),J,0,0
S:Fspi1_master$_SOCON5$0$0({1}SX:U),J,0,0
S:Fspi1_master$_SOCON6$0$0({1}SX:U),J,0,0
S:Fspi1_master$_SOCON7$0$0({1}SX:U),J,0,0
S:Fspi1_master$P2_0$0$0({1}SX:U),J,0,0
S:Fspi1_master$P2_1$0$0({1}SX:U),J,0,0
S:Fspi1_master$P2_2$0$0({1}SX:U),J,0,0
S:Fspi1_master$P2_3$0$0({1}SX:U),J,0,0
S:Fspi1_master$P2_4$0$0({1}SX:U),J,0,0
S:Fspi1_master$P2_5$0$0({1}SX:U),J,0,0
S:Fspi1_master$P2_6$0$0({1}SX:U),J,0,0
S:Fspi1_master$P2_7$0$0({1}SX:U),J,0,0
S:Fspi1_master$RFTXRXIE$0$0({1}SX:U),J,0,0
S:Fspi1_master$ADCIE$0$0({1}SX:U),J,0,0
S:Fspi1_master$URX0IE$0$0({1}SX:U),J,0,0
S:Fspi1_master$URX1IE$0$0({1}SX:U),J,0,0
S:Fspi1_master$ENCIE$0$0({1}SX:U),J,0,0
S:Fspi1_master$STIE$0$0({1}SX:U),J,0,0
S:Fspi1_master$_IEN06$0$0({1}SX:U),J,0,0
S:Fspi1_master$EA$0$0({1}SX:U),J,0,0
S:Fspi1_master$DMAIE$0$0({1}SX:U),J,0,0
S:Fspi1_master$T1IE$0$0({1}SX:U),J,0,0
S:Fspi1_master$T2IE$0$0({1}SX:U),J,0,0
S:Fspi1_master$T3IE$0$0({1}SX:U),J,0,0
S:Fspi1_master$T4IE$0$0({1}SX:U),J,0,0
S:Fspi1_master$P0IE$0$0({1}SX:U),J,0,0
S:Fspi1_master$_IEN16$0$0({1}SX:U),J,0,0
S:Fspi1_master$_IEN17$0$0({1}SX:U),J,0,0
S:Fspi1_master$DMAIF$0$0({1}SX:U),J,0,0
S:Fspi1_master$T1IF$0$0({1}SX:U),J,0,0
S:Fspi1_master$T2IF$0$0({1}SX:U),J,0,0
S:Fspi1_master$T3IF$0$0({1}SX:U),J,0,0
S:Fspi1_master$T4IF$0$0({1}SX:U),J,0,0
S:Fspi1_master$P0IF$0$0({1}SX:U),J,0,0
S:Fspi1_master$_IRCON6$0$0({1}SX:U),J,0,0
S:Fspi1_master$STIF$0$0({1}SX:U),J,0,0
S:Fspi1_master$P$0$0({1}SX:U),J,0,0
S:Fspi1_master$F1$0$0({1}SX:U),J,0,0
S:Fspi1_master$OV$0$0({1}SX:U),J,0,0
S:Fspi1_master$RS0$0$0({1}SX:U),J,0,0
S:Fspi1_master$RS1$0$0({1}SX:U),J,0,0
S:Fspi1_master$F0$0$0({1}SX:U),J,0,0
S:Fspi1_master$AC$0$0({1}SX:U),J,0,0
S:Fspi1_master$CY$0$0({1}SX:U),J,0,0
S:Fspi1_master$T3OVFIF$0$0({1}SX:U),J,0,0
S:Fspi1_master$T3CH0IF$0$0({1}SX:U),J,0,0
S:Fspi1_master$T3CH1IF$0$0({1}SX:U),J,0,0
S:Fspi1_master$T4OVFIF$0$0({1}SX:U),J,0,0
S:Fspi1_master$T4CH0IF$0$0({1}SX:U),J,0,0
S:Fspi1_master$T4CH1IF$0$0({1}SX:U),J,0,0
S:Fspi1_master$OVFIM$0$0({1}SX:U),J,0,0
S:Fspi1_master$_TIMIF7$0$0({1}SX:U),J,0,0
S:Fspi1_master$ACC_0$0$0({1}SX:U),J,0,0
S:Fspi1_master$ACC_1$0$0({1}SX:U),J,0,0
S:Fspi1_master$ACC_2$0$0({1}SX:U),J,0,0
S:Fspi1_master$ACC_3$0$0({1}SX:U),J,0,0
S:Fspi1_master$ACC_4$0$0({1}SX:U),J,0,0
S:Fspi1_master$ACC_5$0$0({1}SX:U),J,0,0
S:Fspi1_master$ACC_6$0$0({1}SX:U),J,0,0
S:Fspi1_master$ACC_7$0$0({1}SX:U),J,0,0
S:Fspi1_master$P2IF$0$0({1}SX:U),J,0,0
S:Fspi1_master$UTX0IF$0$0({1}SX:U),J,0,0
S:Fspi1_master$UTX1IF$0$0({1}SX:U),J,0,0
S:Fspi1_master$P1IF$0$0({1}SX:U),J,0,0
S:Fspi1_master$WDTIF$0$0({1}SX:U),J,0,0
S:Fspi1_master$_IRCON25$0$0({1}SX:U),J,0,0
S:Fspi1_master$_IRCON26$0$0({1}SX:U),J,0,0
S:Fspi1_master$_IRCON27$0$0({1}SX:U),J,0,0
S:Fspi1_master$B_0$0$0({1}SX:U),J,0,0
S:Fspi1_master$B_1$0$0({1}SX:U),J,0,0
S:Fspi1_master$B_2$0$0({1}SX:U),J,0,0
S:Fspi1_master$B_3$0$0({1}SX:U),J,0,0
S:Fspi1_master$B_4$0$0({1}SX:U),J,0,0
S:Fspi1_master$B_5$0$0({1}SX:U),J,0,0
S:Fspi1_master$B_6$0$0({1}SX:U),J,0,0
S:Fspi1_master$B_7$0$0({1}SX:U),J,0,0
S:Fspi1_master$U1ACTIVE$0$0({1}SX:U),J,0,0
S:Fspi1_master$U1TX_BYTE$0$0({1}SX:U),J,0,0
S:Fspi1_master$U1RX_BYTE$0$0({1}SX:U),J,0,0
S:Fspi1_master$U1ERR$0$0({1}SX:U),J,0,0
S:Fspi1_master$U1FE$0$0({1}SX:U),J,0,0
S:Fspi1_master$U1SLAVE$0$0({1}SX:U),J,0,0
S:Fspi1_master$U1RE$0$0({1}SX:U),J,0,0
S:Fspi1_master$U1MODE$0$0({1}SX:U),J,0,0