;!FILE libraries/src/spi_master/spi0_master.asm
XH
H 1B areas 2E5 global symbols
M spi0_master
O -mmcs51 --model-medium
S Fspi0_master$RFIF$0$0 Def00E9
S Fspi0_master$ACC$0$0 Def00E0
S Fspi0_master$P0INP$0$0 Def008F
S Fspi0_master$PA_TABLE0$0$0 DefDF2E
S Fspi0_master$FOCCFG$0$0 DefDF15
S Fspi0_master$_TCON_6$0$0 Def008E
S Fspi0_master$ADC$0$0 DefFFFFBBBA
S Fspi0_master$P1INP$0$0 Def00F6
S Fspi0_master$T1CTL$0$0 Def00E4
S Fspi0_master$P2INP$0$0 Def00F7
S Fspi0_master$FCTL$0$0 Def00AE
S Fspi0_master$FADDRH$0$0 Def00AD
S Fspi0_master$T2CTL$0$0 Def009E
S Fspi0_master$T3CTL$0$0 Def00CB
S Fspi0_master$DEVIATN$0$0 DefDF11
S Fspi0_master$T4CTL$0$0 Def00EB
S Fspi0_master$T3CNT$0$0 Def00CA
S Fspi0_master$RNDH$0$0 Def00BD
S Fspi0_master$IEN0$0$0 Def00A8
S Fspi0_master$DPH0$0$0 Def0083
S __divulong_PARM_2 Ref0000
S Fspi0_master$SYNC0$0$0 DefDF01
S Fspi0_master$T4CNT$0$0 Def00EA
S Fspi0_master$IEN1$0$0 Def00B8
S Fspi0_master$FADDRL$0$0 Def00AC
S Fspi0_master$U0CSR$0$0 Def0086
S Fspi0_master$DPH1$0$0 Def0085
S Fspi0_master$I2SCFG0$0$0 DefDF40
S Fspi0_master$SYNC1$0$0 DefDF00
S Fspi0_master$P0IE$0$0 Def00BD
S Fspi0_master$U1CSR$0$0 Def00F8
S Fspi0_master$IEN2$0$0 Def009A
S Fspi0_master$RFIM$0$0 Def0091
S Fspi0_master$I2SDATH$0$0 DefDF43
S Fspi0_master$I2SCFG1$0$0 DefDF41
S Fspi0_master$U1ERR$0$0 Def00FB
S Fspi0_master$_TIMIF7$0$0 Def00DF
S Fspi0_master$P0IF$0$0 Def00C5
S Fspi0_master$P0_0$0$0 Def0080
S Fspi0_master$U0UCR$0$0 Def00C4
S Fspi0_master$ENDIAN$0$0 Def0095
S Fspi0_master$TEST0$0$0 DefDF25
S Fspi0_master$P1IF$0$0 Def00EB
S Fspi0_master$P$0$0 Def00D0
S Fspi0_master$_IRCON6$0$0 Def00C6
S Fspi0_master$P1_0$0$0 Def0090
S Fspi0_master$P0_1$0$0 Def0081
S Fspi0_master$U1UCR$0$0 Def00FB
S Fspi0_master$RNDL$0$0 Def00BC
S Fspi0_master$PCON$0$0 Def0087
S Fspi0_master$DPL0$0$0 Def0082
S Fspi0_master$USBCSIH$0$0 DefDE12
S Fspi0_master$TEST1$0$0 DefDF24
S Fspi0_master$U1FE$0$0 Def00FC
S Fspi0_master$B_0$0$0 Def00F0
S Fspi0_master$P2IF$0$0 Def00E8
S Fspi0_master$T3CH0IF$0$0 Def00D9
S Fspi0_master$P2_0$0$0 Def00A0
S Fspi0_master$P1_1$0$0 Def0091
S Fspi0_master$P0_2$0$0 Def0082
S Fspi0_master$DPL1$0$0 Def0084
S Fspi0_master$TEST2$0$0 DefDF23
S Fspi0_master$B_1$0$0 Def00F1
S Fspi0_master$T4CH0IF$0$0 Def00DC
S Fspi0_master$T3CH1IF$0$0 Def00DA
S Fspi0_master$P2_1$0$0 Def00A1
S Fspi0_master$P1_2$0$0 Def0092
S Fspi0_master$P0_3$0$0 Def0083
S Fspi0_master$DMAARM$0$0 Def00D6
S Fspi0_master$I2SDATL$0$0 DefDF42
S Fspi0_master$PKTSTATUS$0$0 DefDF3C
S Fspi0_master$B_2$0$0 Def00F2
S Fspi0_master$T4CH1IF$0$0 Def00DD
S Fspi0_master$T1IE$0$0 Def00B9
S Fspi0_master$P2_2$0$0 Def00A2
S Fspi0_master$_SOCON2$0$0 Def009A
S Fspi0_master$P1_3$0$0 Def0093
S Fspi0_master$P0_4$0$0 Def0084
S Fspi0_master$PKTCTRL0$0$0 DefDF04
S Fspi0_master$B_3$0$0 Def00F3
S Fspi0_master$T1IF$0$0 Def00C1
S Fspi0_master$T2IE$0$0 Def00BA
S Fspi0_master$P2_3$0$0 Def00A3
S Fspi0_master$_SOCON3$0$0 Def009B
S Fspi0_master$P1_4$0$0 Def0094
S Fspi0_master$P0_5$0$0 Def0085
S Fspi0_master$TCON$0$0 Def0088
S Fspi0_master$USBCSIL$0$0 DefDE11
S Fspi0_master$PKTCTRL1$0$0 DefDF03
S Fspi0_master$B_4$0$0 Def00F4
S Fspi0_master$T2IF$0$0 Def00C2
S Fspi0_master$T3IE$0$0 Def00BB
S Fspi0_master$STIE$0$0 Def00AD
S Fspi0_master$P2_4$0$0 Def00A4
S Fspi0_master$_SOCON4$0$0 Def009C
S Fspi0_master$P1_5$0$0 Def0095
S Fspi0_master$P0_6$0$0 Def0086
S Fspi0_master$B_5$0$0 Def00F5
S Fspi0_master$ACC_0$0$0 Def00E0
S Fspi0_master$STIF$0$0 Def00C7
S Fspi0_master$T3IF$0$0 Def00C3
S Fspi0_master$T4IE$0$0 Def00BC
S Fspi0_master$ADCIE$0$0 Def00A9
S Fspi0_master$P2_5$0$0 Def00A5
S Fspi0_master$_SOCON5$0$0 Def009D
S Fspi0_master$P1_6$0$0 Def0096
S Fspi0_master$P0_7$0$0 Def0087
S Fspi0_master$USBCNTH$0$0 DefDE17
S Fspi0_master$USBCSOH$0$0 DefDE15
S Fspi0_master$USBFRMH$0$0 DefDE0D
S Fspi0_master$B_6$0$0 Def00F6
S Fspi0_master$ACC_1$0$0 Def00E1
S Fspi0_master$T4IF$0$0 Def00C4
S Fspi0_master$P2_6$0$0 Def00A6
S Fspi0_master$_SOCON6$0$0 Def009E
S Fspi0_master$P1_7$0$0 Def0097
S Fspi0_master$ADCIF$0$0 Def008D
S Fspi0_master$PERCFG$0$0 Def00F1
S Fspi0_master$FWDATA$0$0 Def00AF
S Fspi0_master$WORTIME0$0$0 Def00A5
S Fspi0_master$IOCFG0$0$0 DefDF31
S Fspi0_master$B_7$0$0 Def00F7
S Fspi0_master$ACC_2$0$0 Def00E2
S Fspi0_master$P2_7$0$0 Def00A7
S Fspi0_master$_SOCON7$0$0 Def009F
S Fspi0_master$WORTIME1$0$0 Def00A6
S Fspi0_master$USBMAXI$0$0 DefDE10
S Fspi0_master$IOCFG1$0$0 DefDF30
S Fspi0_master$FSCAL0$0$0 DefDF1F
S Fspi0_master$ACC_3$0$0 Def00E3
S Fspi0_master$FREQEST$0$0 DefDF38
S Fspi0_master$IOCFG2$0$0 DefDF2F
S Fspi0_master$FSCAL1$0$0 DefDF1E
S Fspi0_master$CHANNR$0$0 DefDF06
S Fspi0_master$ACC_4$0$0 Def00E4
S Fspi0_master$DMAREQ$0$0 Def00D7
S Fspi0_master$DMA0CFGH$0$0 Def00D5
S Fspi0_master$CLKCON$0$0 Def00C6
S Fspi0_master$USBCNTL$0$0 DefDE16
S Fspi0_master$USBCSOL$0$0 DefDE14
S Fspi0_master$USBFRML$0$0 DefDE0C
S Fspi0_master$USBCIE$0$0 DefDE0B
S Fspi0_master$FSCAL2$0$0 DefDF1D
S Fspi0_master$ACC_5$0$0 Def00E5
S Fspi0_master$T1CCTL0$0$0 Def00E5
S Fspi0_master$DMA1CFGH$0$0 Def00D3
S Fspi0_master$USBCIF$0$0 DefDE06
S Fspi0_master$FSCAL3$0$0 DefDF1C
S Fspi0_master$ACC_6$0$0 Def00E6
S Fspi0_master$RFTXRXIE$0$0 Def00A8
S Fspi0_master$T1CCTL1$0$0 Def00E6
S Fspi0_master$RFD$0$0 Def00D9
S Fspi0_master$U1RE$0$0 Def00FE
S Fspi0_master$ACC_7$0$0 Def00E7
S Fspi0_master$RFTXRXIF$0$0 Def0089
S Fspi0_master$T1CCTL2$0$0 Def00E7
S Fspi0_master$T3CCTL0$0$0 Def00CC
S Fspi0_master$T2CT$0$0 Def009C
S Fspi0_master$FSCTRL0$0$0 DefDF08
S Fspi0_master$T4CCTL0$0$0 Def00EC
S Fspi0_master$DMA0CFGL$0$0 Def00D4
S Fspi0_master$DMAIRQ$0$0 Def00D1
S Fspi0_master$T3CCTL1$0$0 Def00CE
S Fspi0_master$USBMAXO$0$0 DefDE13
S Fspi0_master$FREND0$0$0 DefDF1B
S Fspi0_master$FSCTRL1$0$0 DefDF07
S Fspi0_master$T4CCTL1$0$0 Def00EE
S Fspi0_master$RFST$0$0 Def00E1
S Fspi0_master$DMA1CFGL$0$0 Def00D2
S Fspi0_master$FREND1$0$0 DefDF1A
S Fspi0_master$DMAIE$0$0 Def00B8
S Fspi0_master$USBIIE$0$0 DefDE07
S Fspi0_master$RSSI$0$0 DefDF3A
S Fspi0_master$U1SLAVE$0$0 Def00FD
S Fspi0_master$T3OVFIF$0$0 Def00D8
S Fspi0_master$DMAIF$0$0 Def00C0
S Fspi0_master$_IEN06$0$0 Def00AE
S Fspi0_master$FADDR$0$0 DefFFFFADAC
S Fspi0_master$U0BAUD$0$0 Def00C2
S Fspi0_master$USBIIF$0$0 DefDE02
S Fspi0_master$T4OVFIF$0$0 Def00DB
S Fspi0_master$_IEN16$0$0 Def00BE
S Fspi0_master$U1BAUD$0$0 Def00FA
S __mullong_PARM_2 Ref0000
S Fspi0_master$_IEN17$0$0 Def00BF
S Fspi0_master$T1CC0H$0$0 Def00DB
S Fspi0_master$ENCDI$0$0 Def00B1
S Fspi0_master$MARCSTATE$0$0 DefDF3B
S Fspi0_master$AC$0$0 Def00D6
S Fspi0_master$ENCIE$0$0 Def00AC
S Fspi0_master$T1CC1H$0$0 Def00DD
S Fspi0_master$BSCFG$0$0 DefDF16
S Fspi0_master$T1CC2H$0$0 Def00DF
S Fspi0_master$LQI$0$0 DefDF39
S Fspi0_master$VERSION$0$0 DefDF37
S Fspi0_master$EA$0$0 Def00AF
S Fspi0_master$U0DBUF$0$0 Def00C1
S Fspi0_master$USBOIE$0$0 DefDE09
S Fspi0_master$VCO_VC_DAC$0$0 DefDF3D
S Fspi0_master$PARTNUM$0$0 DefDF36
S Fspi0_master$U1DBUF$0$0 Def00F9
S Fspi0_master$T1CC0L$0$0 Def00DA
S Fspi0_master$DPS$0$0 Def0092
S Fspi0_master$USBOIF$0$0 DefDE04
S Fspi0_master$T1CC1L$0$0 Def00DC
S Fspi0_master$MEMCTR$0$0 Def00C7
S Fspi0_master$T2PR$0$0 Def009D
S Fspi0_master$T1CC2L$0$0 Def00DE
S Fspi0_master$ENCDO$0$0 Def00B2
S Fspi0_master$IP0$0$0 Def00A9
S Fspi0_master$I2SSTAT$0$0 DefDF45
S Fspi0_master$I2SWCNT$0$0 DefDF44
S Fspi0_master$IP1$0$0 Def00B9
S Fspi0_master$MPAGE$0$0 Def0093
S Fspi0_master$U1MODE$0$0 Def00FF
S Fspi0_master$ENCCS$0$0 Def00B3
S __divulong Ref0000
S Fspi0_master$IRCON2$0$0 Def00E8
S Fspi0_master$WORCTRL$0$0 Def00A2
S Fspi0_master$PKTLEN$0$0 DefDF02
S Fspi0_master$AGCCTRL0$0$0 DefDF19
S Fspi0_master$ADCH$0$0 Def00BB
S Fspi0_master$AGCCTRL1$0$0 DefDF18
S Fspi0_master$FWT$0$0 Def00AB
S Fspi0_master$AGCCTRL2$0$0 DefDF17
S Fspi0_master$DMA0CFG$0$0 DefFFFFD5D4
S Fspi0_master$T1CNTH$0$0 Def00E3
S Fspi0_master$DMA1CFG$0$0 DefFFFFD3D2
S Fspi0_master$ENCIF_0$0$0 Def0098
S Fspi0_master$ADCL$0$0 Def00BA
S Fspi0_master$RS0$0$0 Def00D3
S Fspi0_master$ENCIF_1$0$0 Def0099
S Fspi0_master$F0$0$0 Def00D5
S Fspi0_master$RS1$0$0 Def00D4
S Fspi0_master$T1CNTL$0$0 Def00E2
S Fspi0_master$P0IFG$0$0 Def0089
S Fspi0_master$F1$0$0 Def00D1
S Fspi0_master$WOREVT0$0$0 Def00A3
S Fspi0_master$P1IFG$0$0 Def008A
S Fspi0_master$ADCCFG$0$0 Def00F2
S Fspi0_master$WOREVT1$0$0 Def00A4
S Fspi0_master$P2IFG$0$0 Def008B
S Fspi0_master$TIMIF$0$0 Def00D8
S Fspi0_master$SLEEP$0$0 Def00BE
S Fspi0_master$ADCCON1$0$0 Def00B4
S Fspi0_master$PSW$0$0 Def00D0
S Fspi0_master$ADCCON2$0$0 Def00B5
S Fspi0_master$ADDR$0$0 DefDF05
S Fspi0_master$T1CC0$0$0 DefFFFFDBDA
S Fspi0_master$IRCON$0$0 Def00C0
S Fspi0_master$ADCCON3$0$0 Def00B6
S Fspi0_master$CY$0$0 Def00D7
S Fspi0_master$T1CC1$0$0 DefFFFFDDDC
S Fspi0_master$PICTL$0$0 Def008C
S Fspi0_master$URX0IE$0$0 Def00AA
S Fspi0_master$T1CC2$0$0 DefFFFFDFDE
S Fspi0_master$T3CC0$0$0 Def00CD
S Fspi0_master$P1IEN$0$0 Def008D
S Fspi0_master$I2SCLKF0$0$0 DefDF46
S Fspi0_master$MDMCFG0$0$0 DefDF10
S Fspi0_master$FREQ0$0$0 DefDF0B
S Fspi0_master$WDTIF$0$0 Def00EC
S Fspi0_master$URX1IE$0$0 Def00AB
S Fspi0_master$URX0IF$0$0 Def008B
S Fspi0_master$T4CC0$0$0 Def00ED
S Fspi0_master$T3CC1$0$0 Def00CF
S Fspi0_master$WDCTL$0$0 Def00C9
S Fspi0_master$I2SCLKF1$0$0 DefDF47
S Fspi0_master$MDMCFG1$0$0 DefDF0F
S Fspi0_master$FREQ1$0$0 DefDF0A
S Fspi0_master$URX1IF$0$0 Def008F
S Fspi0_master$P0DIR$0$0 Def00FD
S Fspi0_master$T4CC1$0$0 Def00EF
S Fspi0_master$USBF0$0$0 DefDE20
S Fspi0_master$USBPOW$0$0 DefDE01
S Fspi0_master$I2SCLKF2$0$0 DefDF48
S Fspi0_master$MCSM0$0$0 DefDF14
S Fspi0_master$MDMCFG2$0$0 DefDF0E
S Fspi0_master$FREQ2$0$0 DefDF09
S Fspi0_master$UTX0IF$0$0 Def00E9
S Fspi0_master$P1DIR$0$0 Def00FE
S Fspi0_master$P0$0$0 Def0080
S Fspi0_master$USBF1$0$0 DefDE22
S Fspi0_master$MCSM1$0$0 DefDF13
S Fspi0_master$MDMCFG3$0$0 DefDF0D
S Fspi0_master$_IRCON25$0$0 Def00ED
S Fspi0_master$UTX1IF$0$0 Def00EA
S Fspi0_master$OVFIM$0$0 Def00DE
S Fspi0_master$P2DIR$0$0 Def00FF
S Fspi0_master$U0GCR$0$0 Def00C5
S Fspi0_master$P1$0$0 Def0090
S Fspi0_master$USBF2$0$0 DefDE24
S Fspi0_master$USBINDEX$0$0 DefDE0E
S Fspi0_master$MCSM2$0$0 DefDF12
S Fspi0_master$MDMCFG4$0$0 DefDF0C
S Fspi0_master$U1ACTIVE$0$0 Def00F8
S Fspi0_master$_IRCON26$0$0 Def00EE
S Fspi0_master$_TCON_0$0$0 Def0088
S Fspi0_master$U1GCR$0$0 Def00FC
S Fspi0_master$B$0$0 Def00F0
S Fspi0_master$P2$0$0 Def00A0
S __mullong Ref0000
S Fspi0_master$USBF3$0$0 DefDE26
S Fspi0_master$U1RX_BYTE$0$0 Def00FA
S Fspi0_master$_IRCON27$0$0 Def00EF
S Fspi0_master$S0CON$0$0 Def0098
S Fspi0_master$SP$0$0 Def0081
S Fspi0_master$USBF4$0$0 DefDE28
S Fspi0_master$_TCON_2$0$0 Def008A
S Fspi0_master$P0SEL$0$0 Def00F3
S Fspi0_master$WORIRQ$0$0 Def00A1
S Fspi0_master$S1CON$0$0 Def009B
S Fspi0_master$USBF5$0$0 DefDE2A
S Fspi0_master$USBADDR$0$0 DefDE00
S Fspi0_master$U1TX_BYTE$0$0 Def00F9
S Fspi0_master$OV$0$0 Def00D2
S Fspi0_master$P1SEL$0$0 Def00F4
S .__.ABS. Def0000
S Fspi0_master$_TCON_4$0$0 Def008C
S Fspi0_master$P2SEL$0$0 Def00F5
A _CODE size 0 flags 0 addr 0
A RSEG size 0 flags 8 addr 0
A RSEG0 size 0 flags 8 addr 0
A RSEG1 size 0 flags 8 addr 0
A REG_BANK_0 size 8 flags 4 addr 0
A DSEG size A flags 0 addr 0
S Lspi0MasterSetFrequency$sloc0$1$0 Def0006
S Fspi0_master$rxPointer$0$0 Def0002
S Fspi0_master$txPointer$0$0 Def0000
S Fspi0_master$bytesLeft$0$0 Def0004
A OSEG size 0 flags 4 addr 0
A ISEG size 0 flags 0 addr 0
A IABS size 0 flags 8 addr 0
A BSEG size 3 flags 80 addr 0
S Lspi0MasterSetClockPolarity$polarity$1$1 Def0000
S Lspi0MasterSetBitOrder$bitOrder$1$1 Def0002
S _spi0MasterSetClockPolarity_PARM_1 Def0000
S _spi0MasterSetBitOrder_PARM_1 Def0002
S _spi0MasterSetClockPhase_PARM_1 Def0001
S Lspi0MasterSetClockPhase$phase$1$1 Def0001
A PSEG size 4 flags 50 addr 0
S Lspi0MasterTransfer$rxBuffer$1$1 Def0000
S Lspi0MasterTransfer$size$1$1 Def0002
S _spi0MasterTransfer_PARM_2 Def0000
S _spi0MasterTransfer_PARM_3 Def0002
A XSEG size 2 flags 40 addr 0
S Lspi0MasterSendByte$byte$1$1 Def0000
S Lspi0MasterSendByte$rxByte$1$1 Def0001
A XABS size 0 flags 48 addr 0
A XISEG size 0 flags 40 addr 0
A HOME size 0 flags 20 addr 0
A GSINIT0 size 0 flags 20 addr 0
A GSINIT1 size 0 flags 20 addr 0
A GSINIT2 size 0 flags 20 addr 0
A GSINIT3 size 0 flags 20 addr 0
A GSINIT4 size 0 flags 20 addr 0
A GSINIT5 size 0 flags 20 addr 0
A GSINIT size F flags 20 addr 0
S A$spi0_master$770 Def0006
S A$spi0_master$771 Def0008
S A$spi0_master$763 Def0000
S A$spi0_master$764 Def0001
S A$spi0_master$765 Def0003
S A$spi0_master$775 Def000A
S A$spi0_master$776 Def000B
S C$spi0_master.c$61$1$1 Def000A
S A$spi0_master$777 Def000D
S A$spi0_master$769 Def0005
S C$spi0_master.c$55$1$1 Def0000
S C$spi0_master.c$58$1$1 Def0005
A GSFINAL size 0 flags 20 addr 0
A CSEG size 1DF flags 20 addr 0
S XG$spi0MasterBytesLeft$0$0 Def0137
S _spi0MasterSendByte Def0167
S _spi0MasterSetFrequency Def0014
S G$spi0MasterSetClockPolarity$0$0 Def0103
S XG$spi0MasterReceiveByte$0$0 Def0191
S _spi0MasterTransfer Def0138
S G$spi0MasterBytesLeft$0$0 Def0127
S _spi0MasterSetBitOrder Def0119
S _spi0MasterSetClockPhase Def010E
S A$spi0_master$1000 Def00E4
S XG$spi0MasterSendByte$0$0 Def018B
S XG$spi0MasterSetFrequency$0$0 Def0102
S A$spi0_master$1010 Def00EB
S A$spi0_master$1001 Def00E5
S G$spi0MasterReceiveByte$0$0 Def018E
S A$spi0_master$1200 Def0157
S A$spi0_master$1101 Def0119
S A$spi0_master$1020 Def00F5
S A$spi0_master$1011 Def00EC
S A$spi0_master$1002 Def00E6
S A$spi0_master$1201 Def0159
S A$spi0_master$1030 Def00FD
S A$spi0_master$1021 Def00F6
S A$spi0_master$1012 Def00ED
S A$spi0_master$1003 Def00E7
S A$spi0_master$1310 Def01B0
S A$spi0_master$1301 Def01A1
S A$spi0_master$1202 Def015A
S A$spi0_master$1112 Def0123
S A$spi0_master$1031 Def00FE
S A$spi0_master$1022 Def00F7
S A$spi0_master$1013 Def00EE
S A$spi0_master$1004 Def00E8
S A$spi0_master$1302 Def01A4
S A$spi0_master$1230 Def0167
S A$spi0_master$1212 Def0164
S A$spi0_master$1203 Def015B
S A$spi0_master$1104 Def011C
S A$spi0_master$1023 Def00F8
S A$spi0_master$1014 Def00EF
S A$spi0_master$1321 Def01BB
S A$spi0_master$1303 Def01A7
S A$spi0_master$1240 Def0176
S A$spi0_master$1231 Def0169
S A$spi0_master$1150 Def012D
S A$spi0_master$1105 Def011F
S A$spi0_master$1051 Def0103
S A$spi0_master$1015 Def00F0
S A$spi0_master$1322 Def01BD
S A$spi0_master$1304 Def01A9
S A$spi0_master$1232 Def016C
S A$spi0_master$1151 Def012E
S A$spi0_master$1034 Def0100
S A$spi0_master$1016 Def00F1
S A$spi0_master$1007 Def00EA
S XG$spi0MasterTransfer$0$0 Def0166
S A$spi0_master$1341 Def01D4
S A$spi0_master$1323 Def01BF
S A$spi0_master$1314 Def01B2
S A$spi0_master$1206 Def015D
S A$spi0_master$1161 Def0137
S A$spi0_master$1152 Def012F
S A$spi0_master$1143 Def0127
S A$spi0_master$1080 Def0114
S A$spi0_master$1062 Def010D
S A$spi0_master$1017 Def00F2
S G$spi0MasterSendByte$0$0 Def0167
S G$spi0MasterSetFrequency$0$0 Def0014
S A$spi0_master$1333 Def01C9
S A$spi0_master$1315 Def01B4
S A$spi0_master$1261 Def018B
S A$spi0_master$1252 Def0181
S A$spi0_master$1243 Def0179
S A$spi0_master$1216 Def0166
S A$spi0_master$1207 Def015F
S A$spi0_master$1180 Def0141
S A$spi0_master$1153 Def0131
S A$spi0_master$1126 Def0124
S A$spi0_master$1054 Def0106
S A$spi0_master$1027 Def00FA
S A$spi0_master$1018 Def00F3
S XG$spi0MasterSetBitOrder$0$0 Def0123
S A$spi0_master$1343 Def01D6
S A$spi0_master$1334 Def01CC
S A$spi0_master$1316 Def01B6
S A$spi0_master$1307 Def01AA
S A$spi0_master$1262 Def018D
S A$spi0_master$1253 Def0183
S A$spi0_master$1244 Def017C
S A$spi0_master$1235 Def016D
S A$spi0_master$1208 Def0161
S A$spi0_master$1190 Def014B
S A$spi0_master$1181 Def0142
S A$spi0_master$1109 Def0120
S A$spi0_master$1055 Def0109
S A$spi0_master$1037 Def0102
S A$spi0_master$1019 Def00F4
S _ISR_URX0 Def0194
S _spi0MasterInit Def0000
S A$spi0_master$1344 Def01D8
S A$spi0_master$1335 Def01CF
S A$spi0_master$1326 Def01C1
S A$spi0_master$1317 Def01B9
S A$spi0_master$1308 Def01AC
S A$spi0_master$1254 Def0185
S A$spi0_master$1245 Def017D
S A$spi0_master$1236 Def0170
S A$spi0_master$1209 Def0162
S A$spi0_master$1191 Def014D
S A$spi0_master$1182 Def0143
S A$spi0_master$1173 Def0138
S A$spi0_master$1146 Def0129
S XG$spi0MasterSetClockPhase$0$0 Def0118
S A$spi0_master$1345 Def01DA
S A$spi0_master$1336 Def01D0
S A$spi0_master$1327 Def01C3
S A$spi0_master$1309 Def01AD
S A$spi0_master$1291 Def0194
S A$spi0_master$1192 Def014E
S A$spi0_master$1183 Def0145
S A$spi0_master$1174 Def013A
S A$spi0_master$1147 Def012B
S A$spi0_master$1129 Def0126
S A$spi0_master$1084 Def0115
S A$spi0_master$1346 Def01DC
S A$spi0_master$1337 Def01D2
S A$spi0_master$1328 Def01C4
S A$spi0_master$1292 Def0196
S A$spi0_master$1193 Def0150
S A$spi0_master$1157 Def0133
S A$spi0_master$1076 Def010E
S A$spi0_master$1329 Def01C7
S A$spi0_master$1293 Def0198
S A$spi0_master$1257 Def0187
S A$spi0_master$1248 Def017F
S A$spi0_master$1239 Def0173
S A$spi0_master$1194 Def0151
S A$spi0_master$1158 Def0135
S A$spi0_master$1059 Def010A
S C$spi0_master.c$200$1$1 Def0137
S A$spi0_master$1294 Def019A
S A$spi0_master$1276 Def018E
S A$spi0_master$1258 Def018A
S A$spi0_master$1195 Def0152
S A$spi0_master$1186 Def0147
S A$spi0_master$1177 Def013C
S A$spi0_master$1087 Def0118
S G$spi0MasterTransfer$0$0 Def0138
S C$spi0_master.c$111$1$1 Def0009
S C$spi0_master.c$102$1$1 Def0006
S A$spi0_master$1349 Def01DE
S A$spi0_master$1295 Def019C
S A$spi0_master$1187 Def0149
S A$spi0_master$1178 Def013E
S A$spi0_master$1079 Def0111
S C$spi0_master.c$220$1$1 Def0173
S C$spi0_master.c$202$1$1 Def0138
S C$spi0_master.c$112$1$1 Def000C
S A$spi0_master$1179 Def013F
S C$spi0_master.c$210$2$2 Def015D
S G$spi0MasterSetBitOrder$0$0 Def0119
S A$spi0_master$1279 Def0191
S A$spi0_master$1198 Def0154
S C$spi0_master.c$240$1$1 Def01B2
S C$spi0_master.c$231$1$1 Def018E
S C$spi0_master.c$222$1$1 Def0179
S C$spi0_master.c$211$2$2 Def0164
S C$spi0_master.c$204$1$1 Def013C
S C$spi0_master.c$130$2$2 Def0048
S C$spi0_master.c$114$1$1 Def000F
S A$spi0_master$1298 Def019F
S A$spi0_master$1199 Def0156
S C$spi0_master.c$232$1$1 Def0191
S C$spi0_master.c$223$1$1 Def017F
S C$spi0_master.c$213$2$1 Def0166
S G$spi0MasterSetClockPhase$0$0 Def010E
S C$spi0_master.c$151$1$1 Def0103
S C$spi0_master.c$131$2$2 Def0049
S C$spi0_master.c$124$1$1 Def001B
S C$spi0_master.c$115$1$1 Def0011
S C$spi0_master.c$251$1$1 Def01DE
S C$spi0_master.c$242$1$1 Def01BB
S C$spi0_master.c$161$1$1 Def010E
S C$spi0_master.c$125$1$1 Def0037
S C$spi0_master.c$116$1$1 Def0013
S C$spi0_master.c$234$1$1 Def0194
S C$spi0_master.c$225$1$1 Def0181
S C$spi0_master.c$215$2$1 Def0167
S C$spi0_master.c$171$1$1 Def0118
S C$spi0_master.c$144$1$1 Def00FA
S C$spi0_master.c$141$2$3 Def00EA
S XG$ISR_URX0$0$0 Def01DE
S C$spi0_master.c$226$1$1 Def0187
S C$spi0_master.c$206$2$2 Def0147
S C$spi0_master.c$190$1$1 Def0127
S C$spi0_master.c$163$1$1 Def010E
S C$spi0_master.c$145$1$1 Def00FD
S C$spi0_master.c$142$2$3 Def00EB
S C$spi0_master.c$136$1$1 Def0058
S C$spi0_master.c$118$1$1 Def0014
S XG$spi0MasterInit$0$0 Def0013
S C$spi0_master.c$236$1$1 Def019F
S C$spi0_master.c$227$1$1 Def018B
S C$spi0_master.c$207$2$2 Def014B
S C$spi0_master.c$173$1$1 Def0119
S C$spi0_master.c$153$2$2 Def0106
S C$spi0_master.c$146$1$1 Def0100
S C$spi0_master.c$128$1$1 Def0038
S A$spi0_master$900 Def0052
S C$spi0_master.c$244$2$2 Def01C1
S C$spi0_master.c$219$1$1 Def016D
S C$spi0_master.c$208$2$2 Def0154
S C$spi0_master.c$183$1$1 Def0123
S C$spi0_master.c$147$1$1 Def0102
S A$spi0_master$910 Def005B
S A$spi0_master$901 Def0053
S A$spi0_master$820 Def000C
S A$spi0_master$811 Def0003
S C$spi0_master.c$245$2$2 Def01C9
S C$spi0_master.c$238$1$1 Def01A1
S C$spi0_master.c$229$1$1 Def018E
S C$spi0_master.c$181$2$3 Def0120
S C$spi0_master.c$175$1$1 Def0119
S C$spi0_master.c$139$1$1 Def00DD
S _spi0MasterBusy Def0124
S A$spi0_master$920 Def0065
S A$spi0_master$911 Def005C
S A$spi0_master$902 Def0054
S C$spi0_master.c$239$1$1 Def01AA
S C$spi0_master.c$185$1$1 Def0124
S C$spi0_master.c$165$2$2 Def0111
S C$spi0_master.c$149$1$1 Def0103
S A$spi0_master$930 Def007B
S A$spi0_master$921 Def0068
S A$spi0_master$912 Def005D
S A$spi0_master$903 Def0055
S C$spi0_master.c$195$1$1 Def0127
S C$spi0_master.c$159$1$1 Def010D
S A$spi0_master$940 Def0090
S A$spi0_master$931 Def007E
S A$spi0_master$922 Def0069
S A$spi0_master$913 Def005E
S A$spi0_master$904 Def0056
S A$spi0_master$850 Def001D
S A$spi0_master$823 Def000F
S A$spi0_master$814 Def0006
S C$spi0_master.c$196$1$1 Def0129
S C$spi0_master.c$187$1$1 Def0124
S C$spi0_master.c$157$2$3 Def010A
S A$spi0_master$950 Def009A
S A$spi0_master$941 Def0091
S A$spi0_master$932 Def0081
S A$spi0_master$923 Def006B
S A$spi0_master$914 Def005F
S A$spi0_master$860 Def002D
S A$spi0_master$851 Def001F
S A$spi0_master$842 Def0014
S C$spi0_master.c$197$1$1 Def012D
S C$spi0_master.c$188$1$1 Def0126
S C$spi0_master.c$177$2$2 Def011C
S A$spi0_master$960 Def00AE
S A$spi0_master$951 Def009D
S A$spi0_master$942 Def0092
S A$spi0_master$933 Def0083
S A$spi0_master$924 Def006D
S A$spi0_master$915 Def0060
S A$spi0_master$870 Def0037
S A$spi0_master$861 Def002F
S A$spi0_master$852 Def0020
S A$spi0_master$843 Def0016
S C$spi0_master.c$249$2$3 Def01D4
S G$spi0MasterInit$0$0 Def0000
S G$ISR_URX0$0$0 Def0194
S A$spi0_master$970 Def00BA
S A$spi0_master$961 Def00B0
S A$spi0_master$952 Def009E
S A$spi0_master$943 Def0093
S A$spi0_master$934 Def0085
S A$spi0_master$925 Def006F
S A$spi0_master$916 Def0061
S A$spi0_master$880 Def0040
S A$spi0_master$862 Def0030
S A$spi0_master$853 Def0022
S A$spi0_master$844 Def0018
S A$spi0_master$826 Def0011
S A$spi0_master$817 Def0009
S A$spi0_master$808 Def0000
S C$spi0_master.c$199$1$1 Def0133
S C$spi0_master.c$169$2$3 Def0115
S A$spi0_master$980 Def00CD
S A$spi0_master$971 Def00BC
S A$spi0_master$962 Def00B1
S A$spi0_master$953 Def00A0
S A$spi0_master$944 Def0094
S A$spi0_master$935 Def0087
S A$spi0_master$926 Def0071
S A$spi0_master$917 Def0062
S A$spi0_master$908 Def0058
S A$spi0_master$881 Def0041
S A$spi0_master$863 Def0032
S A$spi0_master$854 Def0023
S A$spi0_master$845 Def001A
S A$spi0_master$990 Def00DA
S A$spi0_master$981 Def00CE
S A$spi0_master$972 Def00BE
S A$spi0_master$963 Def00B2
S A$spi0_master$954 Def00A2
S A$spi0_master$945 Def0095
S A$spi0_master$936 Def0089
S A$spi0_master$927 Def0073
S A$spi0_master$918 Def0063
S A$spi0_master$909 Def005A
S A$spi0_master$891 Def0049
S A$spi0_master$882 Def0043
S A$spi0_master$864 Def0033
S A$spi0_master$855 Def0025
S A$spi0_master$991 Def00DC
S A$spi0_master$982 Def00D0
S A$spi0_master$973 Def00C0
S A$spi0_master$964 Def00B4
S A$spi0_master$955 Def00A5
S A$spi0_master$946 Def0096
S A$spi0_master$937 Def008B
S A$spi0_master$928 Def0075
S A$spi0_master$919 Def0064
S A$spi0_master$892 Def004A
S A$spi0_master$883 Def0044
S A$spi0_master$874 Def0038
S A$spi0_master$865 Def0034
S A$spi0_master$856 Def0026
S A$spi0_master$829 Def0013
S _spi0MasterSetClockPolarity Def0103
S A$spi0_master$983 Def00D1
S A$spi0_master$974 Def00C1
S A$spi0_master$965 Def00B5
S A$spi0_master$956 Def00A7
S A$spi0_master$947 Def0097
S A$spi0_master$938 Def008D
S A$spi0_master$929 Def0078
S A$spi0_master$893 Def004B
S A$spi0_master$884 Def0045
S A$spi0_master$866 Def0035
S A$spi0_master$857 Def0028
S A$spi0_master$848 Def001B
S C$spi0_master.c$63$0$0 Def0000
S A$spi0_master$984 Def00D2
S A$spi0_master$975 Def00C4
S A$spi0_master$966 Def00B6
S A$spi0_master$957 Def00A9
S A$spi0_master$948 Def0098
S A$spi0_master$939 Def008F
S A$spi0_master$894 Def004C
S A$spi0_master$885 Def0046
S A$spi0_master$876 Def003A
S A$spi0_master$858 Def002A
S A$spi0_master$849 Def001C
S A$spi0_master$985 Def00D4
S A$spi0_master$976 Def00C6
S A$spi0_master$967 Def00B7
S A$spi0_master$958 Def00AB
S A$spi0_master$949 Def0099
S A$spi0_master$895 Def004D
S A$spi0_master$877 Def003B
S A$spi0_master$859 Def002C
S XG$spi0MasterBusy$0$0 Def0126
S C$spi0_master.c$90$1$1 Def0000
S A$spi0_master$995 Def00DD
S A$spi0_master$986 Def00D5
S A$spi0_master$977 Def00C8
S A$spi0_master$968 Def00B8
S A$spi0_master$959 Def00AC
S A$spi0_master$896 Def004E
S A$spi0_master$878 Def003D
S C$spi0_master.c$91$1$1 Def0003
S A$spi0_master$996 Def00DE
S A$spi0_master$987 Def00D6
S A$spi0_master$978 Def00CA
S A$spi0_master$969 Def00B9
S A$spi0_master$897 Def004F
S A$spi0_master$888 Def0048
S A$spi0_master$879 Def003E
S A$spi0_master$997 Def00E0
S A$spi0_master$988 Def00D8
S A$spi0_master$979 Def00CB
S A$spi0_master$898 Def0050
S _spi0MasterBytesLeft Def0127
S A$spi0_master$998 Def00E1
S A$spi0_master$989 Def00D9
S A$spi0_master$899 Def0051
S A$spi0_master$999 Def00E3
S G$spi0MasterBusy$0$0 Def0124
S _spi0MasterReceiveByte Def018E
S XG$spi0MasterSetClockPolarity$0$0 Def010D
A CONST size 0 flags 20 addr 0
A XINIT size 0 flags 20 addr 0
A CABS size 0 flags 28 addr 0
T 00 00
R 00 00 00 02
T 00 00
R 00 00 00 03
T 00 00
R 00 00 00 04
T 00 00
R 00 00 00 05
T 00 00
R 00 00 00 05
T 00 02
R 00 00 00 05
T 00 02
R 00 00 00 05
T 00 04
R 00 00 00 05
T 00 04
R 00 00 00 05
T 00 06
R 00 00 00 05
T 00 06
R 00 00 00 05
T 00 00
R 00 00 00 09
T 00 00
R 00 00 00 09
T 00 01
R 00 00 00 09
T 00 01
R 00 00 00 09
T 00 02
R 00 00 00 09
T 00 02
R 00 00 00 09
T 00 00
R 00 00 00 0A
T 00 00
R 00 00 00 0A
T 00 02
R 00 00 00 0A
T 00 02
R 00 00 00 0A
T 00 00
R 00 00 00 0B
T 00 00
R 00 00 00 0B
T 00 01
R 00 00 00 0B
T 00 01
R 00 00 00 0B
T 00 00 E4 F5 00 00 00 F5 00 00 01 E4 F5
R 00 00 00 15 F1 21 04 00 05 F1 21 08 00 05
T 00 07 00 00 02 F5 00 00 03 E4 F5
R 00 00 00 15 F1 21 02 00 05 F1 21 06 00 05
T 00 0C 00 00 04 F5 00 00 05
R 00 00 00 15 F1 21 02 00 05 F1 21 06 00 05
T 00 00
R 00 00 00 17
T 00 00 53 FF 3F 53 F1 FE 43 F3 28 43 A9 04 53 B9
R 00 00 00 17
T 00 0E FB C2 8B D2 AF 22
R 00 00 00 17
T 00 14
R 00 00 00 17
T 00 14 AA 82 AB 83 AC F0 FD C3 EA 94 17 EB 94 00
R 00 00 00 17
T 00 22 EC 94 00 ED 94 00 40 0D 74 C0 9A 74 C6 9B
R 00 00 00 17
T 00 30 74 2D 9C E4 9D 50 01
R 00 00 00 17
T 00 37
R 00 00 00 17
T 00 37 22
R 00 00 00 17
T 00 38
R 00 00 00 17
T 00 38 7E 00
R 00 00 00 17
T 00 3A
R 00 00 00 17
T 00 3A C3 74 A6 9A 74 90 9B 74 07 9C E4 9D 50 10
R 00 00 00 17
T 00 48 0E ED C3 13 FD EC 13 FC EB 13 FB EA 13 FA
R 00 00 00 17
T 00 56 80 E2
R 00 00 00 17
T 00 58
R 00 00 00 17
T 00 58 78 00 00 00 EA F2 08 EB F2 08 EC F2 08 ED
R 00 00 00 17 F1 03 03 00 B7
T 00 64 F2 90 00 0B E4 F5 F0 C0 02 C0 03 C0 04 C0
R 00 00 00 17
T 00 72 05 C0 06 12 00 00 85 82 00 00 06 85 83
R 00 00 00 17 02 06 01 2D F1 21 0A 00 05
T 00 7D 00 00 07 85 F0 00 00 08 F5
R 00 00 00 17 F1 21 02 00 05 F1 21 07 00 05
T 00 82 00 00 09 D0 06 D0 05 D0 04 D0 03 D0 02 78
R 00 00 00 17 F1 21 02 00 05
T 00 8E 00 00 00 EA F2 08 EB F2 08 EC F2 08 ED F2
R 00 00 00 17 F1 03 02 00 B7
T 00 9A 90 21 D7 E4 F5 F0 C0 06 12 00 00 AC 82 AD
R 00 00 00 17 02 0B 01 2D
T 00 A8 83 AA F0 FB 78 00 00 00 74 1B F2 08 74 B7
R 00 00 00 17 F1 03 07 00 14
T 00 B4 F2 08 E4 F2 08 F2 8C 82 8D 83 8A F0 EB 12
R 00 00 00 17
T 00 C2 00 00 AA 82 AB 83 AC F0 FD D0 06 EA 25
R 00 00 00 17 02 02 00 D8
T 00 CF 00 00 06 FA EB 35 00 00 07 FB EC 35
R 00 00 00 17 F1 21 02 00 05 F1 21 08 00 05
T 00 D7 00 00 08 FC ED 35 00 00 09 FD
R 00 00 00 17 F1 21 02 00 05 F1 21 08 00 05
T 00 DD
R 00 00 00 17
T 00 DD C3 74 FF 9A 74 01 9B E4 9C E4 9D 50 10 0E
R 00 00 00 17
T 00 EB ED C3 13 FD EC 13 FC EB 13 FB EA 13 FA 80
R 00 00 00 17
T 00 F9 E3
R 00 00 00 17
T 00 FA
R 00 00 00 17
T 00 FA 53 C5 E0 EE 42 C5 8A C2 22
R 00 00 00 17
T 01 03
R 00 00 00 17
T 01 03 20 00 00 00 04 53 C5 7F 22
R 00 00 00 17 F1 21 03 00 09
T 01 0A
R 00 00 00 17
T 01 0A 43 C5 80 22
R 00 00 00 17
T 01 0E
R 00 00 00 17
T 01 0E 20 00 00 01 04 53 C5 BF 22
R 00 00 00 17 F1 21 03 00 09
T 01 15
R 00 00 00 17
T 01 15 43 C5 40 22
R 00 00 00 17
T 01 19
R 00 00 00 17
T 01 19 30 00 00 02 04 53 C5 DF 22
R 00 00 00 17 F1 21 03 00 09
T 01 20
R 00 00 00 17
T 01 20 43 C5 20 22
R 00 00 00 17
T 01 24
R 00 00 00 17
T 01 24 A2 AA 22
R 00 00 00 17
T 01 27
R 00 00 00 17
T 01 27 C2 AA AA 00 00 04 AB 00 00 05 EA 4B 60 02
R 00 00 00 17 F1 21 05 00 05 F1 21 09 00 05
T 01 31 D2 AA
R 00 00 00 17
T 01 33
R 00 00 00 17
T 01 33 8A 82 8B 83 22
R 00 00 00 17
T 01 38
R 00 00 00 17
T 01 38 AA 82 AB 83 78 00 00 02 E2 F5 F0 08 E2 45
R 00 00 00 17 F1 01 07 00 0A
T 01 44 F0 60 1F 8A 00 00 00 8B 00 00 01 78
R 00 00 00 17 F1 21 06 00 05 F1 21 0A 00 05
T 01 4C 00 00 00 E2 F5 00 00 02 08 E2 F5
R 00 00 00 17 F1 01 02 00 0A F1 21 07 00 05
T 01 53 00 00 03 78 00 00 02 E2 F5
R 00 00 00 17 F1 21 02 00 05 F1 01 06 00 0A
T 01 58 00 00 04 08 E2 F5 00 00 05 8A 82 8B 83 E0
R 00 00 00 17 F1 21 02 00 05 F1 21 08 00 05
T 01 62 F5 C1 D2 AA
R 00 00 00 17
T 01 66
R 00 00 00 17
T 01 66 22
R 00 00 00 17
T 01 67
R 00 00 00 17
T 01 67 E5 82 90 00 00 F0 75 00 00 02
R 00 00 00 17 00 05 00 0B F1 21 09 00 05
T 01 6F 00 00 01 75 00 00 03
R 00 00 00 17 F1 01 02 00 0B F1 21 06 00 05
T 01 72 00 00 01 75 00 00 04 01 75
R 00 00 00 17 F1 81 02 00 0B F1 21 06 00 05
T 01 77 00 00 05 00 90 00 00 E0 F5 C1 D2 AA
R 00 00 00 17 F1 21 02 00 05 00 07 00 0B
T 01 81
R 00 00 00 17
T 01 81 E5 00 00 04 45 00 00 05 70 FA 90
R 00 00 00 17 F1 21 03 00 05 F1 21 07 00 05
T 01 88 00 01 E0 F5 82 22
R 00 00 00 17 00 02 00 0B
T 01 8E
R 00 00 00 17
T 01 8E 75 82 FF 02 01 67
R 00 00 00 17 00 06 00 17
T 01 94
R 00 00 00 17
T 01 94 C0 E0 C0 82 C0 83 C0 D0 75 D0 00 C2 8B 85
R 00 00 00 17
T 01 A2 00 00 02 82 85 00 00 03 83 E5 C1 F0 05
R 00 00 00 17 F1 21 02 00 05 F1 21 07 00 05
T 01 AB 00 00 02 E4 B5 00 00 02 02 05
R 00 00 00 17 F1 21 02 00 05 F1 21 07 00 05
T 01 B1 00 00 03
R 00 00 00 17 F1 21 02 00 05
T 01 B2
R 00 00 00 17
T 01 B2 15 00 00 04 74 FF B5 00 00 04 02 15
R 00 00 00 17 F1 21 03 00 05 F1 21 09 00 05
T 01 BA 00 00 05
R 00 00 00 17 F1 21 02 00 05
T 01 BB
R 00 00 00 17
T 01 BB E5 00 00 04 45 00 00 05 60 13 05
R 00 00 00 17 F1 21 03 00 05 F1 21 07 00 05
T 01 C2 00 00 00 E4 B5 00 00 00 02 05
R 00 00 00 17 F1 21 02 00 05 F1 21 07 00 05
T 01 C8 00 00 01
R 00 00 00 17 F1 21 02 00 05
T 01 C9
R 00 00 00 17
T 01 C9 85 00 00 00 82 85 00 00 01 83 E0 F5 C1 80
R 00 00 00 17 F1 21 03 00 05 F1 21 08 00 05
T 01 D3 02
R 00 00 00 17
T 01 D4
R 00 00 00 17
T 01 D4 C2 AA
R 00 00 00 17
T 01 D6
R 00 00 00 17
T 01 D6 D0 D0 D0 83 D0 82 D0 E0 32
R 00 00 00 17