;-------------------------------------------------------- ; File Created by SDCC : free open source ANSI-C Compiler ; Version 3.0.0 #6037 (Oct 31 2010) (Linux) ; This file was generated Sun Feb 26 03:56:10 2012 ;-------------------------------------------------------- .module spi0_master .optsdcc -mmcs51 --model-medium ;-------------------------------------------------------- ; Public variables in this module ;-------------------------------------------------------- .globl _spi0MasterTransfer_PARM_3 .globl _spi0MasterTransfer_PARM_2 .globl _spi0MasterSetBitOrder_PARM_1 .globl _spi0MasterSetClockPhase_PARM_1 .globl _spi0MasterSetClockPolarity_PARM_1 .globl _spi0MasterInit .globl _spi0MasterSetFrequency .globl _spi0MasterSetClockPolarity .globl _spi0MasterSetClockPhase .globl _spi0MasterSetBitOrder .globl _spi0MasterBusy .globl _spi0MasterBytesLeft .globl _spi0MasterTransfer .globl _spi0MasterSendByte .globl _spi0MasterReceiveByte .globl _ISR_URX0 ;-------------------------------------------------------- ; special function registers ;-------------------------------------------------------- .area RSEG (ABS,DATA) .org 0x0000 Fspi0_master$P0$0$0 == 0x0080 _P0 = 0x0080 Fspi0_master$SP$0$0 == 0x0081 _SP = 0x0081 Fspi0_master$DPL0$0$0 == 0x0082 _DPL0 = 0x0082 Fspi0_master$DPH0$0$0 == 0x0083 _DPH0 = 0x0083 Fspi0_master$DPL1$0$0 == 0x0084 _DPL1 = 0x0084 Fspi0_master$DPH1$0$0 == 0x0085 _DPH1 = 0x0085 Fspi0_master$U0CSR$0$0 == 0x0086 _U0CSR = 0x0086 Fspi0_master$PCON$0$0 == 0x0087 _PCON = 0x0087 Fspi0_master$TCON$0$0 == 0x0088 _TCON = 0x0088 Fspi0_master$P0IFG$0$0 == 0x0089 _P0IFG = 0x0089 Fspi0_master$P1IFG$0$0 == 0x008a _P1IFG = 0x008a Fspi0_master$P2IFG$0$0 == 0x008b _P2IFG = 0x008b Fspi0_master$PICTL$0$0 == 0x008c _PICTL = 0x008c Fspi0_master$P1IEN$0$0 == 0x008d _P1IEN = 0x008d Fspi0_master$P0INP$0$0 == 0x008f _P0INP = 0x008f Fspi0_master$P1$0$0 == 0x0090 _P1 = 0x0090 Fspi0_master$RFIM$0$0 == 0x0091 _RFIM = 0x0091 Fspi0_master$DPS$0$0 == 0x0092 _DPS = 0x0092 Fspi0_master$MPAGE$0$0 == 0x0093 _MPAGE = 0x0093 Fspi0_master$ENDIAN$0$0 == 0x0095 _ENDIAN = 0x0095 Fspi0_master$S0CON$0$0 == 0x0098 _S0CON = 0x0098 Fspi0_master$IEN2$0$0 == 0x009a _IEN2 = 0x009a Fspi0_master$S1CON$0$0 == 0x009b _S1CON = 0x009b Fspi0_master$T2CT$0$0 == 0x009c _T2CT = 0x009c Fspi0_master$T2PR$0$0 == 0x009d _T2PR = 0x009d Fspi0_master$T2CTL$0$0 == 0x009e _T2CTL = 0x009e Fspi0_master$P2$0$0 == 0x00a0 _P2 = 0x00a0 Fspi0_master$WORIRQ$0$0 == 0x00a1 _WORIRQ = 0x00a1 Fspi0_master$WORCTRL$0$0 == 0x00a2 _WORCTRL = 0x00a2 Fspi0_master$WOREVT0$0$0 == 0x00a3 _WOREVT0 = 0x00a3 Fspi0_master$WOREVT1$0$0 == 0x00a4 _WOREVT1 = 0x00a4 Fspi0_master$WORTIME0$0$0 == 0x00a5 _WORTIME0 = 0x00a5 Fspi0_master$WORTIME1$0$0 == 0x00a6 _WORTIME1 = 0x00a6 Fspi0_master$IEN0$0$0 == 0x00a8 _IEN0 = 0x00a8 Fspi0_master$IP0$0$0 == 0x00a9 _IP0 = 0x00a9 Fspi0_master$FWT$0$0 == 0x00ab _FWT = 0x00ab Fspi0_master$FADDRL$0$0 == 0x00ac _FADDRL = 0x00ac Fspi0_master$FADDRH$0$0 == 0x00ad _FADDRH = 0x00ad Fspi0_master$FCTL$0$0 == 0x00ae _FCTL = 0x00ae Fspi0_master$FWDATA$0$0 == 0x00af _FWDATA = 0x00af Fspi0_master$ENCDI$0$0 == 0x00b1 _ENCDI = 0x00b1 Fspi0_master$ENCDO$0$0 == 0x00b2 _ENCDO = 0x00b2 Fspi0_master$ENCCS$0$0 == 0x00b3 _ENCCS = 0x00b3 Fspi0_master$ADCCON1$0$0 == 0x00b4 _ADCCON1 = 0x00b4 Fspi0_master$ADCCON2$0$0 == 0x00b5 _ADCCON2 = 0x00b5 Fspi0_master$ADCCON3$0$0 == 0x00b6 _ADCCON3 = 0x00b6 Fspi0_master$IEN1$0$0 == 0x00b8 _IEN1 = 0x00b8 Fspi0_master$IP1$0$0 == 0x00b9 _IP1 = 0x00b9 Fspi0_master$ADCL$0$0 == 0x00ba _ADCL = 0x00ba Fspi0_master$ADCH$0$0 == 0x00bb _ADCH = 0x00bb Fspi0_master$RNDL$0$0 == 0x00bc _RNDL = 0x00bc Fspi0_master$RNDH$0$0 == 0x00bd _RNDH = 0x00bd Fspi0_master$SLEEP$0$0 == 0x00be _SLEEP = 0x00be Fspi0_master$IRCON$0$0 == 0x00c0 _IRCON = 0x00c0 Fspi0_master$U0DBUF$0$0 == 0x00c1 _U0DBUF = 0x00c1 Fspi0_master$U0BAUD$0$0 == 0x00c2 _U0BAUD = 0x00c2 Fspi0_master$U0UCR$0$0 == 0x00c4 _U0UCR = 0x00c4 Fspi0_master$U0GCR$0$0 == 0x00c5 _U0GCR = 0x00c5 Fspi0_master$CLKCON$0$0 == 0x00c6 _CLKCON = 0x00c6 Fspi0_master$MEMCTR$0$0 == 0x00c7 _MEMCTR = 0x00c7 Fspi0_master$WDCTL$0$0 == 0x00c9 _WDCTL = 0x00c9 Fspi0_master$T3CNT$0$0 == 0x00ca _T3CNT = 0x00ca Fspi0_master$T3CTL$0$0 == 0x00cb _T3CTL = 0x00cb Fspi0_master$T3CCTL0$0$0 == 0x00cc _T3CCTL0 = 0x00cc Fspi0_master$T3CC0$0$0 == 0x00cd _T3CC0 = 0x00cd Fspi0_master$T3CCTL1$0$0 == 0x00ce _T3CCTL1 = 0x00ce Fspi0_master$T3CC1$0$0 == 0x00cf _T3CC1 = 0x00cf Fspi0_master$PSW$0$0 == 0x00d0 _PSW = 0x00d0 Fspi0_master$DMAIRQ$0$0 == 0x00d1 _DMAIRQ = 0x00d1 Fspi0_master$DMA1CFGL$0$0 == 0x00d2 _DMA1CFGL = 0x00d2 Fspi0_master$DMA1CFGH$0$0 == 0x00d3 _DMA1CFGH = 0x00d3 Fspi0_master$DMA0CFGL$0$0 == 0x00d4 _DMA0CFGL = 0x00d4 Fspi0_master$DMA0CFGH$0$0 == 0x00d5 _DMA0CFGH = 0x00d5 Fspi0_master$DMAARM$0$0 == 0x00d6 _DMAARM = 0x00d6 Fspi0_master$DMAREQ$0$0 == 0x00d7 _DMAREQ = 0x00d7 Fspi0_master$TIMIF$0$0 == 0x00d8 _TIMIF = 0x00d8 Fspi0_master$RFD$0$0 == 0x00d9 _RFD = 0x00d9 Fspi0_master$T1CC0L$0$0 == 0x00da _T1CC0L = 0x00da Fspi0_master$T1CC0H$0$0 == 0x00db _T1CC0H = 0x00db Fspi0_master$T1CC1L$0$0 == 0x00dc _T1CC1L = 0x00dc Fspi0_master$T1CC1H$0$0 == 0x00dd _T1CC1H = 0x00dd Fspi0_master$T1CC2L$0$0 == 0x00de _T1CC2L = 0x00de Fspi0_master$T1CC2H$0$0 == 0x00df _T1CC2H = 0x00df Fspi0_master$ACC$0$0 == 0x00e0 _ACC = 0x00e0 Fspi0_master$RFST$0$0 == 0x00e1 _RFST = 0x00e1 Fspi0_master$T1CNTL$0$0 == 0x00e2 _T1CNTL = 0x00e2 Fspi0_master$T1CNTH$0$0 == 0x00e3 _T1CNTH = 0x00e3 Fspi0_master$T1CTL$0$0 == 0x00e4 _T1CTL = 0x00e4 Fspi0_master$T1CCTL0$0$0 == 0x00e5 _T1CCTL0 = 0x00e5 Fspi0_master$T1CCTL1$0$0 == 0x00e6 _T1CCTL1 = 0x00e6 Fspi0_master$T1CCTL2$0$0 == 0x00e7 _T1CCTL2 = 0x00e7 Fspi0_master$IRCON2$0$0 == 0x00e8 _IRCON2 = 0x00e8 Fspi0_master$RFIF$0$0 == 0x00e9 _RFIF = 0x00e9 Fspi0_master$T4CNT$0$0 == 0x00ea _T4CNT = 0x00ea Fspi0_master$T4CTL$0$0 == 0x00eb _T4CTL = 0x00eb Fspi0_master$T4CCTL0$0$0 == 0x00ec _T4CCTL0 = 0x00ec Fspi0_master$T4CC0$0$0 == 0x00ed _T4CC0 = 0x00ed Fspi0_master$T4CCTL1$0$0 == 0x00ee _T4CCTL1 = 0x00ee Fspi0_master$T4CC1$0$0 == 0x00ef _T4CC1 = 0x00ef Fspi0_master$B$0$0 == 0x00f0 _B = 0x00f0 Fspi0_master$PERCFG$0$0 == 0x00f1 _PERCFG = 0x00f1 Fspi0_master$ADCCFG$0$0 == 0x00f2 _ADCCFG = 0x00f2 Fspi0_master$P0SEL$0$0 == 0x00f3 _P0SEL = 0x00f3 Fspi0_master$P1SEL$0$0 == 0x00f4 _P1SEL = 0x00f4 Fspi0_master$P2SEL$0$0 == 0x00f5 _P2SEL = 0x00f5 Fspi0_master$P1INP$0$0 == 0x00f6 _P1INP = 0x00f6 Fspi0_master$P2INP$0$0 == 0x00f7 _P2INP = 0x00f7 Fspi0_master$U1CSR$0$0 == 0x00f8 _U1CSR = 0x00f8 Fspi0_master$U1DBUF$0$0 == 0x00f9 _U1DBUF = 0x00f9 Fspi0_master$U1BAUD$0$0 == 0x00fa _U1BAUD = 0x00fa Fspi0_master$U1UCR$0$0 == 0x00fb _U1UCR = 0x00fb Fspi0_master$U1GCR$0$0 == 0x00fc _U1GCR = 0x00fc Fspi0_master$P0DIR$0$0 == 0x00fd _P0DIR = 0x00fd Fspi0_master$P1DIR$0$0 == 0x00fe _P1DIR = 0x00fe Fspi0_master$P2DIR$0$0 == 0x00ff _P2DIR = 0x00ff Fspi0_master$DMA0CFG$0$0 == 0xffffd5d4 _DMA0CFG = 0xffffd5d4 Fspi0_master$DMA1CFG$0$0 == 0xffffd3d2 _DMA1CFG = 0xffffd3d2 Fspi0_master$FADDR$0$0 == 0xffffadac _FADDR = 0xffffadac Fspi0_master$ADC$0$0 == 0xffffbbba _ADC = 0xffffbbba Fspi0_master$T1CC0$0$0 == 0xffffdbda _T1CC0 = 0xffffdbda Fspi0_master$T1CC1$0$0 == 0xffffdddc _T1CC1 = 0xffffdddc Fspi0_master$T1CC2$0$0 == 0xffffdfde _T1CC2 = 0xffffdfde ;-------------------------------------------------------- ; special function bits ;-------------------------------------------------------- .area RSEG (ABS,DATA) .org 0x0000 Fspi0_master$P0_0$0$0 == 0x0080 _P0_0 = 0x0080 Fspi0_master$P0_1$0$0 == 0x0081 _P0_1 = 0x0081 Fspi0_master$P0_2$0$0 == 0x0082 _P0_2 = 0x0082 Fspi0_master$P0_3$0$0 == 0x0083 _P0_3 = 0x0083 Fspi0_master$P0_4$0$0 == 0x0084 _P0_4 = 0x0084 Fspi0_master$P0_5$0$0 == 0x0085 _P0_5 = 0x0085 Fspi0_master$P0_6$0$0 == 0x0086 _P0_6 = 0x0086 Fspi0_master$P0_7$0$0 == 0x0087 _P0_7 = 0x0087 Fspi0_master$_TCON_0$0$0 == 0x0088 __TCON_0 = 0x0088 Fspi0_master$RFTXRXIF$0$0 == 0x0089 _RFTXRXIF = 0x0089 Fspi0_master$_TCON_2$0$0 == 0x008a __TCON_2 = 0x008a Fspi0_master$URX0IF$0$0 == 0x008b _URX0IF = 0x008b Fspi0_master$_TCON_4$0$0 == 0x008c __TCON_4 = 0x008c Fspi0_master$ADCIF$0$0 == 0x008d _ADCIF = 0x008d Fspi0_master$_TCON_6$0$0 == 0x008e __TCON_6 = 0x008e Fspi0_master$URX1IF$0$0 == 0x008f _URX1IF = 0x008f Fspi0_master$P1_0$0$0 == 0x0090 _P1_0 = 0x0090 Fspi0_master$P1_1$0$0 == 0x0091 _P1_1 = 0x0091 Fspi0_master$P1_2$0$0 == 0x0092 _P1_2 = 0x0092 Fspi0_master$P1_3$0$0 == 0x0093 _P1_3 = 0x0093 Fspi0_master$P1_4$0$0 == 0x0094 _P1_4 = 0x0094 Fspi0_master$P1_5$0$0 == 0x0095 _P1_5 = 0x0095 Fspi0_master$P1_6$0$0 == 0x0096 _P1_6 = 0x0096 Fspi0_master$P1_7$0$0 == 0x0097 _P1_7 = 0x0097 Fspi0_master$ENCIF_0$0$0 == 0x0098 _ENCIF_0 = 0x0098 Fspi0_master$ENCIF_1$0$0 == 0x0099 _ENCIF_1 = 0x0099 Fspi0_master$_SOCON2$0$0 == 0x009a __SOCON2 = 0x009a Fspi0_master$_SOCON3$0$0 == 0x009b __SOCON3 = 0x009b Fspi0_master$_SOCON4$0$0 == 0x009c __SOCON4 = 0x009c Fspi0_master$_SOCON5$0$0 == 0x009d __SOCON5 = 0x009d Fspi0_master$_SOCON6$0$0 == 0x009e __SOCON6 = 0x009e Fspi0_master$_SOCON7$0$0 == 0x009f __SOCON7 = 0x009f Fspi0_master$P2_0$0$0 == 0x00a0 _P2_0 = 0x00a0 Fspi0_master$P2_1$0$0 == 0x00a1 _P2_1 = 0x00a1 Fspi0_master$P2_2$0$0 == 0x00a2 _P2_2 = 0x00a2 Fspi0_master$P2_3$0$0 == 0x00a3 _P2_3 = 0x00a3 Fspi0_master$P2_4$0$0 == 0x00a4 _P2_4 = 0x00a4 Fspi0_master$P2_5$0$0 == 0x00a5 _P2_5 = 0x00a5 Fspi0_master$P2_6$0$0 == 0x00a6 _P2_6 = 0x00a6 Fspi0_master$P2_7$0$0 == 0x00a7 _P2_7 = 0x00a7 Fspi0_master$RFTXRXIE$0$0 == 0x00a8 _RFTXRXIE = 0x00a8 Fspi0_master$ADCIE$0$0 == 0x00a9 _ADCIE = 0x00a9 Fspi0_master$URX0IE$0$0 == 0x00aa _URX0IE = 0x00aa Fspi0_master$URX1IE$0$0 == 0x00ab _URX1IE = 0x00ab Fspi0_master$ENCIE$0$0 == 0x00ac _ENCIE = 0x00ac Fspi0_master$STIE$0$0 == 0x00ad _STIE = 0x00ad Fspi0_master$_IEN06$0$0 == 0x00ae __IEN06 = 0x00ae Fspi0_master$EA$0$0 == 0x00af _EA = 0x00af Fspi0_master$DMAIE$0$0 == 0x00b8 _DMAIE = 0x00b8 Fspi0_master$T1IE$0$0 == 0x00b9 _T1IE = 0x00b9 Fspi0_master$T2IE$0$0 == 0x00ba _T2IE = 0x00ba Fspi0_master$T3IE$0$0 == 0x00bb _T3IE = 0x00bb Fspi0_master$T4IE$0$0 == 0x00bc _T4IE = 0x00bc Fspi0_master$P0IE$0$0 == 0x00bd _P0IE = 0x00bd Fspi0_master$_IEN16$0$0 == 0x00be __IEN16 = 0x00be Fspi0_master$_IEN17$0$0 == 0x00bf __IEN17 = 0x00bf Fspi0_master$DMAIF$0$0 == 0x00c0 _DMAIF = 0x00c0 Fspi0_master$T1IF$0$0 == 0x00c1 _T1IF = 0x00c1 Fspi0_master$T2IF$0$0 == 0x00c2 _T2IF = 0x00c2 Fspi0_master$T3IF$0$0 == 0x00c3 _T3IF = 0x00c3 Fspi0_master$T4IF$0$0 == 0x00c4 _T4IF = 0x00c4 Fspi0_master$P0IF$0$0 == 0x00c5 _P0IF = 0x00c5 Fspi0_master$_IRCON6$0$0 == 0x00c6 __IRCON6 = 0x00c6 Fspi0_master$STIF$0$0 == 0x00c7 _STIF = 0x00c7 Fspi0_master$P$0$0 == 0x00d0 _P = 0x00d0 Fspi0_master$F1$0$0 == 0x00d1 _F1 = 0x00d1 Fspi0_master$OV$0$0 == 0x00d2 _OV = 0x00d2 Fspi0_master$RS0$0$0 == 0x00d3 _RS0 = 0x00d3 Fspi0_master$RS1$0$0 == 0x00d4 _RS1 = 0x00d4 Fspi0_master$F0$0$0 == 0x00d5 _F0 = 0x00d5 Fspi0_master$AC$0$0 == 0x00d6 _AC = 0x00d6 Fspi0_master$CY$0$0 == 0x00d7 _CY = 0x00d7 Fspi0_master$T3OVFIF$0$0 == 0x00d8 _T3OVFIF = 0x00d8 Fspi0_master$T3CH0IF$0$0 == 0x00d9 _T3CH0IF = 0x00d9 Fspi0_master$T3CH1IF$0$0 == 0x00da _T3CH1IF = 0x00da Fspi0_master$T4OVFIF$0$0 == 0x00db _T4OVFIF = 0x00db Fspi0_master$T4CH0IF$0$0 == 0x00dc _T4CH0IF = 0x00dc Fspi0_master$T4CH1IF$0$0 == 0x00dd _T4CH1IF = 0x00dd Fspi0_master$OVFIM$0$0 == 0x00de _OVFIM = 0x00de Fspi0_master$_TIMIF7$0$0 == 0x00df __TIMIF7 = 0x00df Fspi0_master$ACC_0$0$0 == 0x00e0 _ACC_0 = 0x00e0 Fspi0_master$ACC_1$0$0 == 0x00e1 _ACC_1 = 0x00e1 Fspi0_master$ACC_2$0$0 == 0x00e2 _ACC_2 = 0x00e2 Fspi0_master$ACC_3$0$0 == 0x00e3 _ACC_3 = 0x00e3 Fspi0_master$ACC_4$0$0 == 0x00e4 _ACC_4 = 0x00e4 Fspi0_master$ACC_5$0$0 == 0x00e5 _ACC_5 = 0x00e5 Fspi0_master$ACC_6$0$0 == 0x00e6 _ACC_6 = 0x00e6 Fspi0_master$ACC_7$0$0 == 0x00e7 _ACC_7 = 0x00e7 Fspi0_master$P2IF$0$0 == 0x00e8 _P2IF = 0x00e8 Fspi0_master$UTX0IF$0$0 == 0x00e9 _UTX0IF = 0x00e9 Fspi0_master$UTX1IF$0$0 == 0x00ea _UTX1IF = 0x00ea Fspi0_master$P1IF$0$0 == 0x00eb _P1IF = 0x00eb Fspi0_master$WDTIF$0$0 == 0x00ec _WDTIF = 0x00ec Fspi0_master$_IRCON25$0$0 == 0x00ed __IRCON25 = 0x00ed Fspi0_master$_IRCON26$0$0 == 0x00ee __IRCON26 = 0x00ee Fspi0_master$_IRCON27$0$0 == 0x00ef __IRCON27 = 0x00ef Fspi0_master$B_0$0$0 == 0x00f0 _B_0 = 0x00f0 Fspi0_master$B_1$0$0 == 0x00f1 _B_1 = 0x00f1 Fspi0_master$B_2$0$0 == 0x00f2 _B_2 = 0x00f2 Fspi0_master$B_3$0$0 == 0x00f3 _B_3 = 0x00f3 Fspi0_master$B_4$0$0 == 0x00f4 _B_4 = 0x00f4 Fspi0_master$B_5$0$0 == 0x00f5 _B_5 = 0x00f5 Fspi0_master$B_6$0$0 == 0x00f6 _B_6 = 0x00f6 Fspi0_master$B_7$0$0 == 0x00f7 _B_7 = 0x00f7 Fspi0_master$U1ACTIVE$0$0 == 0x00f8 _U1ACTIVE = 0x00f8 Fspi0_master$U1TX_BYTE$0$0 == 0x00f9 _U1TX_BYTE = 0x00f9 Fspi0_master$U1RX_BYTE$0$0 == 0x00fa _U1RX_BYTE = 0x00fa Fspi0_master$U1ERR$0$0 == 0x00fb _U1ERR = 0x00fb Fspi0_master$U1FE$0$0 == 0x00fc _U1FE = 0x00fc Fspi0_master$U1SLAVE$0$0 == 0x00fd _U1SLAVE = 0x00fd Fspi0_master$U1RE$0$0 == 0x00fe _U1RE = 0x00fe Fspi0_master$U1MODE$0$0 == 0x00ff _U1MODE = 0x00ff ;-------------------------------------------------------- ; overlayable register banks ;-------------------------------------------------------- .area REG_BANK_0 (REL,OVR,DATA) .ds 8 ;-------------------------------------------------------- ; internal ram data ;-------------------------------------------------------- .area DSEG (DATA) Fspi0_master$txPointer$0$0==. _txPointer: .ds 2 Fspi0_master$rxPointer$0$0==. _rxPointer: .ds 2 Fspi0_master$bytesLeft$0$0==. _bytesLeft: .ds 2 Lspi0MasterSetFrequency$sloc0$1$0==. _spi0MasterSetFrequency_sloc0_1_0: .ds 4 ;-------------------------------------------------------- ; overlayable items in internal ram ;-------------------------------------------------------- .area OSEG (OVR,DATA) ;-------------------------------------------------------- ; indirectly addressable internal ram data ;-------------------------------------------------------- .area ISEG (DATA) ;-------------------------------------------------------- ; absolute internal ram data ;-------------------------------------------------------- .area IABS (ABS,DATA) .area IABS (ABS,DATA) ;-------------------------------------------------------- ; bit data ;-------------------------------------------------------- .area BSEG (BIT) Lspi0MasterSetClockPolarity$polarity$1$1==. _spi0MasterSetClockPolarity_PARM_1: .ds 1 Lspi0MasterSetClockPhase$phase$1$1==. _spi0MasterSetClockPhase_PARM_1: .ds 1 Lspi0MasterSetBitOrder$bitOrder$1$1==. _spi0MasterSetBitOrder_PARM_1: .ds 1 ;-------------------------------------------------------- ; paged external ram data ;-------------------------------------------------------- .area PSEG (PAG,XDATA) Lspi0MasterTransfer$rxBuffer$1$1==. _spi0MasterTransfer_PARM_2: .ds 2 Lspi0MasterTransfer$size$1$1==. _spi0MasterTransfer_PARM_3: .ds 2 ;-------------------------------------------------------- ; external ram data ;-------------------------------------------------------- .area XSEG (XDATA) Fspi0_master$SYNC1$0$0 == 0xdf00 _SYNC1 = 0xdf00 Fspi0_master$SYNC0$0$0 == 0xdf01 _SYNC0 = 0xdf01 Fspi0_master$PKTLEN$0$0 == 0xdf02 _PKTLEN = 0xdf02 Fspi0_master$PKTCTRL1$0$0 == 0xdf03 _PKTCTRL1 = 0xdf03 Fspi0_master$PKTCTRL0$0$0 == 0xdf04 _PKTCTRL0 = 0xdf04 Fspi0_master$ADDR$0$0 == 0xdf05 _ADDR = 0xdf05 Fspi0_master$CHANNR$0$0 == 0xdf06 _CHANNR = 0xdf06 Fspi0_master$FSCTRL1$0$0 == 0xdf07 _FSCTRL1 = 0xdf07 Fspi0_master$FSCTRL0$0$0 == 0xdf08 _FSCTRL0 = 0xdf08 Fspi0_master$FREQ2$0$0 == 0xdf09 _FREQ2 = 0xdf09 Fspi0_master$FREQ1$0$0 == 0xdf0a _FREQ1 = 0xdf0a Fspi0_master$FREQ0$0$0 == 0xdf0b _FREQ0 = 0xdf0b Fspi0_master$MDMCFG4$0$0 == 0xdf0c _MDMCFG4 = 0xdf0c Fspi0_master$MDMCFG3$0$0 == 0xdf0d _MDMCFG3 = 0xdf0d Fspi0_master$MDMCFG2$0$0 == 0xdf0e _MDMCFG2 = 0xdf0e Fspi0_master$MDMCFG1$0$0 == 0xdf0f _MDMCFG1 = 0xdf0f Fspi0_master$MDMCFG0$0$0 == 0xdf10 _MDMCFG0 = 0xdf10 Fspi0_master$DEVIATN$0$0 == 0xdf11 _DEVIATN = 0xdf11 Fspi0_master$MCSM2$0$0 == 0xdf12 _MCSM2 = 0xdf12 Fspi0_master$MCSM1$0$0 == 0xdf13 _MCSM1 = 0xdf13 Fspi0_master$MCSM0$0$0 == 0xdf14 _MCSM0 = 0xdf14 Fspi0_master$FOCCFG$0$0 == 0xdf15 _FOCCFG = 0xdf15 Fspi0_master$BSCFG$0$0 == 0xdf16 _BSCFG = 0xdf16 Fspi0_master$AGCCTRL2$0$0 == 0xdf17 _AGCCTRL2 = 0xdf17 Fspi0_master$AGCCTRL1$0$0 == 0xdf18 _AGCCTRL1 = 0xdf18 Fspi0_master$AGCCTRL0$0$0 == 0xdf19 _AGCCTRL0 = 0xdf19 Fspi0_master$FREND1$0$0 == 0xdf1a _FREND1 = 0xdf1a Fspi0_master$FREND0$0$0 == 0xdf1b _FREND0 = 0xdf1b Fspi0_master$FSCAL3$0$0 == 0xdf1c _FSCAL3 = 0xdf1c Fspi0_master$FSCAL2$0$0 == 0xdf1d _FSCAL2 = 0xdf1d Fspi0_master$FSCAL1$0$0 == 0xdf1e _FSCAL1 = 0xdf1e Fspi0_master$FSCAL0$0$0 == 0xdf1f _FSCAL0 = 0xdf1f Fspi0_master$TEST2$0$0 == 0xdf23 _TEST2 = 0xdf23 Fspi0_master$TEST1$0$0 == 0xdf24 _TEST1 = 0xdf24 Fspi0_master$TEST0$0$0 == 0xdf25 _TEST0 = 0xdf25 Fspi0_master$PA_TABLE0$0$0 == 0xdf2e _PA_TABLE0 = 0xdf2e Fspi0_master$IOCFG2$0$0 == 0xdf2f _IOCFG2 = 0xdf2f Fspi0_master$IOCFG1$0$0 == 0xdf30 _IOCFG1 = 0xdf30 Fspi0_master$IOCFG0$0$0 == 0xdf31 _IOCFG0 = 0xdf31 Fspi0_master$PARTNUM$0$0 == 0xdf36 _PARTNUM = 0xdf36 Fspi0_master$VERSION$0$0 == 0xdf37 _VERSION = 0xdf37 Fspi0_master$FREQEST$0$0 == 0xdf38 _FREQEST = 0xdf38 Fspi0_master$LQI$0$0 == 0xdf39 _LQI = 0xdf39 Fspi0_master$RSSI$0$0 == 0xdf3a _RSSI = 0xdf3a Fspi0_master$MARCSTATE$0$0 == 0xdf3b _MARCSTATE = 0xdf3b Fspi0_master$PKTSTATUS$0$0 == 0xdf3c _PKTSTATUS = 0xdf3c Fspi0_master$VCO_VC_DAC$0$0 == 0xdf3d _VCO_VC_DAC = 0xdf3d Fspi0_master$I2SCFG0$0$0 == 0xdf40 _I2SCFG0 = 0xdf40 Fspi0_master$I2SCFG1$0$0 == 0xdf41 _I2SCFG1 = 0xdf41 Fspi0_master$I2SDATL$0$0 == 0xdf42 _I2SDATL = 0xdf42 Fspi0_master$I2SDATH$0$0 == 0xdf43 _I2SDATH = 0xdf43 Fspi0_master$I2SWCNT$0$0 == 0xdf44 _I2SWCNT = 0xdf44 Fspi0_master$I2SSTAT$0$0 == 0xdf45 _I2SSTAT = 0xdf45 Fspi0_master$I2SCLKF0$0$0 == 0xdf46 _I2SCLKF0 = 0xdf46 Fspi0_master$I2SCLKF1$0$0 == 0xdf47 _I2SCLKF1 = 0xdf47 Fspi0_master$I2SCLKF2$0$0 == 0xdf48 _I2SCLKF2 = 0xdf48 Fspi0_master$USBADDR$0$0 == 0xde00 _USBADDR = 0xde00 Fspi0_master$USBPOW$0$0 == 0xde01 _USBPOW = 0xde01 Fspi0_master$USBIIF$0$0 == 0xde02 _USBIIF = 0xde02 Fspi0_master$USBOIF$0$0 == 0xde04 _USBOIF = 0xde04 Fspi0_master$USBCIF$0$0 == 0xde06 _USBCIF = 0xde06 Fspi0_master$USBIIE$0$0 == 0xde07 _USBIIE = 0xde07 Fspi0_master$USBOIE$0$0 == 0xde09 _USBOIE = 0xde09 Fspi0_master$USBCIE$0$0 == 0xde0b _USBCIE = 0xde0b Fspi0_master$USBFRML$0$0 == 0xde0c _USBFRML = 0xde0c Fspi0_master$USBFRMH$0$0 == 0xde0d _USBFRMH = 0xde0d Fspi0_master$USBINDEX$0$0 == 0xde0e _USBINDEX = 0xde0e Fspi0_master$USBMAXI$0$0 == 0xde10 _USBMAXI = 0xde10 Fspi0_master$USBCSIL$0$0 == 0xde11 _USBCSIL = 0xde11 Fspi0_master$USBCSIH$0$0 == 0xde12 _USBCSIH = 0xde12 Fspi0_master$USBMAXO$0$0 == 0xde13 _USBMAXO = 0xde13 Fspi0_master$USBCSOL$0$0 == 0xde14 _USBCSOL = 0xde14 Fspi0_master$USBCSOH$0$0 == 0xde15 _USBCSOH = 0xde15 Fspi0_master$USBCNTL$0$0 == 0xde16 _USBCNTL = 0xde16 Fspi0_master$USBCNTH$0$0 == 0xde17 _USBCNTH = 0xde17 Fspi0_master$USBF0$0$0 == 0xde20 _USBF0 = 0xde20 Fspi0_master$USBF1$0$0 == 0xde22 _USBF1 = 0xde22 Fspi0_master$USBF2$0$0 == 0xde24 _USBF2 = 0xde24 Fspi0_master$USBF3$0$0 == 0xde26 _USBF3 = 0xde26 Fspi0_master$USBF4$0$0 == 0xde28 _USBF4 = 0xde28 Fspi0_master$USBF5$0$0 == 0xde2a _USBF5 = 0xde2a Lspi0MasterSendByte$byte$1$1==. _spi0MasterSendByte_byte_1_1: .ds 1 Lspi0MasterSendByte$rxByte$1$1==. _spi0MasterSendByte_rxByte_1_1: .ds 1 ;-------------------------------------------------------- ; absolute external ram data ;-------------------------------------------------------- .area XABS (ABS,XDATA) ;-------------------------------------------------------- ; external initialized ram data ;-------------------------------------------------------- .area XISEG (XDATA) .area HOME (CODE) .area GSINIT0 (CODE) .area GSINIT1 (CODE) .area GSINIT2 (CODE) .area GSINIT3 (CODE) .area GSINIT4 (CODE) .area GSINIT5 (CODE) .area GSINIT (CODE) .area GSFINAL (CODE) .area CSEG (CODE) ;-------------------------------------------------------- ; global & static initialisations ;-------------------------------------------------------- .area HOME (CODE) .area GSINIT (CODE) .area GSFINAL (CODE) .area GSINIT (CODE) G$ISR_URX0$0$0 ==. C$spi0_master.c$55$1$1 ==. ; libraries/src/spi_master/spi0_master.c:55: static volatile const uint8 XDATA * DATA txPointer = 0; clr a mov _txPointer,a mov (_txPointer + 1),a G$ISR_URX0$0$0 ==. C$spi0_master.c$58$1$1 ==. ; libraries/src/spi_master/spi0_master.c:58: static volatile uint8 XDATA * DATA rxPointer = 0; clr a mov _rxPointer,a mov (_rxPointer + 1),a G$ISR_URX0$0$0 ==. C$spi0_master.c$61$1$1 ==. ; libraries/src/spi_master/spi0_master.c:61: static volatile uint16 DATA bytesLeft = 0; clr a mov _bytesLeft,a mov (_bytesLeft + 1),a ;-------------------------------------------------------- ; Home ;-------------------------------------------------------- .area HOME (CODE) .area HOME (CODE) ;-------------------------------------------------------- ; code ;-------------------------------------------------------- .area CSEG (CODE) ;------------------------------------------------------------ ;Allocation info for local variables in function 'spi0MasterInit' ;------------------------------------------------------------ ;------------------------------------------------------------ G$spi0MasterInit$0$0 ==. C$spi0_master.c$63$0$0 ==. ; libraries/src/spi_master/spi0_master.c:63: void spiNMasterInit(void) ; ----------------------------------------- ; function spi0MasterInit ; ----------------------------------------- _spi0MasterInit: ar2 = 0x02 ar3 = 0x03 ar4 = 0x04 ar5 = 0x05 ar6 = 0x06 ar7 = 0x07 ar0 = 0x00 ar1 = 0x01 C$spi0_master.c$90$1$1 ==. ; libraries/src/spi_master/spi0_master.c:90: P2DIR &= ~0xC0; // P2DIR.PRIP0 (7:6) = 00 : USART0 takes priority over USART1. anl _P2DIR,#0x3F C$spi0_master.c$91$1$1 ==. ; libraries/src/spi_master/spi0_master.c:91: PERCFG &= ~0x01; // PERCFG.U0CFG (0) = 0 (Alt. 1) : USART0 uses alt. location 1. anl _PERCFG,#0xFE C$spi0_master.c$102$1$1 ==. ; libraries/src/spi_master/spi0_master.c:102: P0SEL |= ((1<<5) | (1<<3)); // P0SEL.SELP0_5 = 1, P0SEL.SELP0_3 = 1 orl _P0SEL,#0x28 C$spi0_master.c$111$1$1 ==. ; libraries/src/spi_master/spi0_master.c:111: IP0 |= (1< 3000000) clr c mov a,r2 subb a,#0x17 mov a,r3 subb a,#0x00 mov a,r4 subb a,#0x00 mov a,r5 subb a,#0x00 jc 00101$ mov a,#0xC0 subb a,r2 mov a,#0xC6 subb a,r3 mov a,#0x2D subb a,r4 clr a subb a,r5 jnc 00114$ 00101$: C$spi0_master.c$125$1$1 ==. ; libraries/src/spi_master/spi0_master.c:125: return; ret C$spi0_master.c$128$1$1 ==. ; libraries/src/spi_master/spi0_master.c:128: while (freq > 495782) 00114$: mov r6,#0x00 00104$: clr c mov a,#0xA6 subb a,r2 mov a,#0x90 subb a,r3 mov a,#0x07 subb a,r4 clr a subb a,r5 jnc 00106$ C$spi0_master.c$130$2$2 ==. ; libraries/src/spi_master/spi0_master.c:130: baudE++; inc r6 C$spi0_master.c$131$2$2 ==. ; libraries/src/spi_master/spi0_master.c:131: freq /= 2; mov a,r5 clr c rrc a mov r5,a mov a,r4 rrc a mov r4,a mov a,r3 rrc a mov r3,a mov a,r2 rrc a mov r2,a sjmp 00104$ 00106$: C$spi0_master.c$136$1$1 ==. ; libraries/src/spi_master/spi0_master.c:136: baudMPlus256 = (freq * 11) + (freq * 8663 / 46875); mov r0,#__mullong_PARM_2 mov a,r2 movx @r0,a inc r0 mov a,r3 movx @r0,a inc r0 mov a,r4 movx @r0,a inc r0 mov a,r5 movx @r0,a mov dptr,#(0x0B&0x00ff) clr a mov b,a push ar2 push ar3 push ar4 push ar5 push ar6 lcall __mullong mov _spi0MasterSetFrequency_sloc0_1_0,dpl mov (_spi0MasterSetFrequency_sloc0_1_0 + 1),dph mov (_spi0MasterSetFrequency_sloc0_1_0 + 2),b mov (_spi0MasterSetFrequency_sloc0_1_0 + 3),a pop ar6 pop ar5 pop ar4 pop ar3 pop ar2 mov r0,#__mullong_PARM_2 mov a,r2 movx @r0,a inc r0 mov a,r3 movx @r0,a inc r0 mov a,r4 movx @r0,a inc r0 mov a,r5 movx @r0,a mov dptr,#0x21D7 clr a mov b,a push ar6 lcall __mullong mov r4,dpl mov r5,dph mov r2,b mov r3,a mov r0,#__divulong_PARM_2 mov a,#0x1B movx @r0,a inc r0 mov a,#0xB7 movx @r0,a inc r0 clr a movx @r0,a inc r0 movx @r0,a mov dpl,r4 mov dph,r5 mov b,r2 mov a,r3 lcall __divulong mov r2,dpl mov r3,dph mov r4,b mov r5,a pop ar6 mov a,r2 add a,_spi0MasterSetFrequency_sloc0_1_0 mov r2,a mov a,r3 addc a,(_spi0MasterSetFrequency_sloc0_1_0 + 1) mov r3,a mov a,r4 addc a,(_spi0MasterSetFrequency_sloc0_1_0 + 2) mov r4,a mov a,r5 addc a,(_spi0MasterSetFrequency_sloc0_1_0 + 3) mov r5,a C$spi0_master.c$139$1$1 ==. ; libraries/src/spi_master/spi0_master.c:139: while (baudMPlus256 > 0x1ff) 00107$: clr c mov a,#0xFF subb a,r2 mov a,#0x01 subb a,r3 clr a subb a,r4 clr a subb a,r5 jnc 00109$ C$spi0_master.c$141$2$3 ==. ; libraries/src/spi_master/spi0_master.c:141: baudE++; inc r6 C$spi0_master.c$142$2$3 ==. ; libraries/src/spi_master/spi0_master.c:142: baudMPlus256 /= 2; mov a,r5 clr c rrc a mov r5,a mov a,r4 rrc a mov r4,a mov a,r3 rrc a mov r3,a mov a,r2 rrc a mov r2,a sjmp 00107$ 00109$: C$spi0_master.c$144$1$1 ==. ; libraries/src/spi_master/spi0_master.c:144: UNGCR &= 0xE0; // preserve CPOL, CPHA, ORDER (7:5) anl _U0GCR,#0xE0 C$spi0_master.c$145$1$1 ==. ; libraries/src/spi_master/spi0_master.c:145: UNGCR |= baudE; // UNGCR.BAUD_E (4:0) mov a,r6 orl _U0GCR,a C$spi0_master.c$146$1$1 ==. ; libraries/src/spi_master/spi0_master.c:146: UNBAUD = baudMPlus256; // UNBAUD.BAUD_M (7:0) - only the lowest 8 bits of baudMPlus256 are used, so this is effectively baudMPlus256 - 256 mov _U0BAUD,r2 C$spi0_master.c$147$1$1 ==. XG$spi0MasterSetFrequency$0$0 ==. ret ;------------------------------------------------------------ ;Allocation info for local variables in function 'spi0MasterSetClockPolarity' ;------------------------------------------------------------ ;------------------------------------------------------------ G$spi0MasterSetClockPolarity$0$0 ==. C$spi0_master.c$149$1$1 ==. ; libraries/src/spi_master/spi0_master.c:149: void spiNMasterSetClockPolarity(BIT polarity) ; ----------------------------------------- ; function spi0MasterSetClockPolarity ; ----------------------------------------- _spi0MasterSetClockPolarity: C$spi0_master.c$151$1$1 ==. ; libraries/src/spi_master/spi0_master.c:151: if (polarity == SPI_POLARITY_IDLE_LOW) jb _spi0MasterSetClockPolarity_PARM_1,00102$ C$spi0_master.c$153$2$2 ==. ; libraries/src/spi_master/spi0_master.c:153: UNGCR &= ~(1<<7); // SCK idle low (negative polarity) anl _U0GCR,#0x7F ret 00102$: C$spi0_master.c$157$2$3 ==. ; libraries/src/spi_master/spi0_master.c:157: UNGCR |= (1<<7); // SCK idle high (positive polarity) orl _U0GCR,#0x80 C$spi0_master.c$159$1$1 ==. XG$spi0MasterSetClockPolarity$0$0 ==. ret ;------------------------------------------------------------ ;Allocation info for local variables in function 'spi0MasterSetClockPhase' ;------------------------------------------------------------ ;------------------------------------------------------------ G$spi0MasterSetClockPhase$0$0 ==. C$spi0_master.c$161$1$1 ==. ; libraries/src/spi_master/spi0_master.c:161: void spiNMasterSetClockPhase(BIT phase) ; ----------------------------------------- ; function spi0MasterSetClockPhase ; ----------------------------------------- _spi0MasterSetClockPhase: C$spi0_master.c$163$1$1 ==. ; libraries/src/spi_master/spi0_master.c:163: if (phase == SPI_PHASE_EDGE_LEADING) jb _spi0MasterSetClockPhase_PARM_1,00102$ C$spi0_master.c$165$2$2 ==. ; libraries/src/spi_master/spi0_master.c:165: UNGCR &= ~(1<<6); // data centered on leading (first) edge - rising for idle low, falling for idle high anl _U0GCR,#0xBF ret 00102$: C$spi0_master.c$169$2$3 ==. ; libraries/src/spi_master/spi0_master.c:169: UNGCR |= (1<<6); // data centered on trailing (second) edge - falling for idle low, rising for idle high orl _U0GCR,#0x40 C$spi0_master.c$171$1$1 ==. XG$spi0MasterSetClockPhase$0$0 ==. ret ;------------------------------------------------------------ ;Allocation info for local variables in function 'spi0MasterSetBitOrder' ;------------------------------------------------------------ ;------------------------------------------------------------ G$spi0MasterSetBitOrder$0$0 ==. C$spi0_master.c$173$1$1 ==. ; libraries/src/spi_master/spi0_master.c:173: void spiNMasterSetBitOrder(BIT bitOrder) ; ----------------------------------------- ; function spi0MasterSetBitOrder ; ----------------------------------------- _spi0MasterSetBitOrder: C$spi0_master.c$175$1$1 ==. ; libraries/src/spi_master/spi0_master.c:175: if (bitOrder == SPI_BIT_ORDER_LSB_FIRST) jnb _spi0MasterSetBitOrder_PARM_1,00102$ C$spi0_master.c$177$2$2 ==. ; libraries/src/spi_master/spi0_master.c:177: UNGCR &= ~(1<<5); // LSB first anl _U0GCR,#0xDF ret 00102$: C$spi0_master.c$181$2$3 ==. ; libraries/src/spi_master/spi0_master.c:181: UNGCR |= (1<<5); // MSB first orl _U0GCR,#0x20 C$spi0_master.c$183$1$1 ==. XG$spi0MasterSetBitOrder$0$0 ==. ret ;------------------------------------------------------------ ;Allocation info for local variables in function 'spi0MasterBusy' ;------------------------------------------------------------ ;------------------------------------------------------------ G$spi0MasterBusy$0$0 ==. C$spi0_master.c$185$1$1 ==. ; libraries/src/spi_master/spi0_master.c:185: BIT spiNMasterBusy(void) ; ----------------------------------------- ; function spi0MasterBusy ; ----------------------------------------- _spi0MasterBusy: C$spi0_master.c$187$1$1 ==. ; libraries/src/spi_master/spi0_master.c:187: return URXNIE; mov c,_URX0IE C$spi0_master.c$188$1$1 ==. XG$spi0MasterBusy$0$0 ==. ret ;------------------------------------------------------------ ;Allocation info for local variables in function 'spi0MasterBytesLeft' ;------------------------------------------------------------ ;------------------------------------------------------------ G$spi0MasterBytesLeft$0$0 ==. C$spi0_master.c$190$1$1 ==. ; libraries/src/spi_master/spi0_master.c:190: uint16 spiNMasterBytesLeft(void) ; ----------------------------------------- ; function spi0MasterBytesLeft ; ----------------------------------------- _spi0MasterBytesLeft: C$spi0_master.c$195$1$1 ==. ; libraries/src/spi_master/spi0_master.c:195: URXNIE = 0; clr _URX0IE C$spi0_master.c$196$1$1 ==. ; libraries/src/spi_master/spi0_master.c:196: bytes = bytesLeft; mov r2,_bytesLeft mov r3,(_bytesLeft + 1) C$spi0_master.c$197$1$1 ==. ; libraries/src/spi_master/spi0_master.c:197: if (bytes) URXNIE = 1; mov a,r2 orl a,r3 jz 00102$ setb _URX0IE 00102$: C$spi0_master.c$199$1$1 ==. ; libraries/src/spi_master/spi0_master.c:199: return bytes; mov dpl,r2 mov dph,r3 C$spi0_master.c$200$1$1 ==. XG$spi0MasterBytesLeft$0$0 ==. ret ;------------------------------------------------------------ ;Allocation info for local variables in function 'spi0MasterTransfer' ;------------------------------------------------------------ ;------------------------------------------------------------ G$spi0MasterTransfer$0$0 ==. C$spi0_master.c$202$1$1 ==. ; libraries/src/spi_master/spi0_master.c:202: void spiNMasterTransfer(const uint8 XDATA * txBuffer, uint8 XDATA * rxBuffer, uint16 size) ; ----------------------------------------- ; function spi0MasterTransfer ; ----------------------------------------- _spi0MasterTransfer: mov r2,dpl mov r3,dph C$spi0_master.c$204$1$1 ==. ; libraries/src/spi_master/spi0_master.c:204: if (size) mov r0,#_spi0MasterTransfer_PARM_3 movx a,@r0 mov b,a inc r0 movx a,@r0 orl a,b jz 00103$ C$spi0_master.c$206$2$2 ==. ; libraries/src/spi_master/spi0_master.c:206: txPointer = txBuffer; mov _txPointer,r2 mov (_txPointer + 1),r3 C$spi0_master.c$207$2$2 ==. ; libraries/src/spi_master/spi0_master.c:207: rxPointer = rxBuffer; mov r0,#_spi0MasterTransfer_PARM_2 movx a,@r0 mov _rxPointer,a inc r0 movx a,@r0 mov (_rxPointer + 1),a C$spi0_master.c$208$2$2 ==. ; libraries/src/spi_master/spi0_master.c:208: bytesLeft = size; mov r0,#_spi0MasterTransfer_PARM_3 movx a,@r0 mov _bytesLeft,a inc r0 movx a,@r0 mov (_bytesLeft + 1),a C$spi0_master.c$210$2$2 ==. ; libraries/src/spi_master/spi0_master.c:210: UNDBUF = *txBuffer; // transmit first byte mov dpl,r2 mov dph,r3 movx a,@dptr mov _U0DBUF,a C$spi0_master.c$211$2$2 ==. ; libraries/src/spi_master/spi0_master.c:211: URXNIE = 1; // Enable RX interrupt. setb _URX0IE 00103$: C$spi0_master.c$213$2$1 ==. XG$spi0MasterTransfer$0$0 ==. ret ;------------------------------------------------------------ ;Allocation info for local variables in function 'spi0MasterSendByte' ;------------------------------------------------------------ ;byte Allocated with name '_spi0MasterSendByte_byte_1_1' ;rxByte Allocated with name '_spi0MasterSendByte_rxByte_1_1' ;------------------------------------------------------------ G$spi0MasterSendByte$0$0 ==. C$spi0_master.c$215$2$1 ==. ; libraries/src/spi_master/spi0_master.c:215: uint8 spiNMasterSendByte(uint8 XDATA byte) ; ----------------------------------------- ; function spi0MasterSendByte ; ----------------------------------------- _spi0MasterSendByte: mov a,dpl mov dptr,#_spi0MasterSendByte_byte_1_1 movx @dptr,a C$spi0_master.c$219$1$1 ==. ; libraries/src/spi_master/spi0_master.c:219: rxPointer = &rxByte; mov _rxPointer,#_spi0MasterSendByte_rxByte_1_1 mov (_rxPointer + 1),#(_spi0MasterSendByte_rxByte_1_1 >> 8) C$spi0_master.c$220$1$1 ==. ; libraries/src/spi_master/spi0_master.c:220: bytesLeft = 1; mov _bytesLeft,#0x01 mov (_bytesLeft + 1),#0x00 C$spi0_master.c$222$1$1 ==. ; libraries/src/spi_master/spi0_master.c:222: UNDBUF = byte; mov dptr,#_spi0MasterSendByte_byte_1_1 movx a,@dptr mov _U0DBUF,a C$spi0_master.c$223$1$1 ==. ; libraries/src/spi_master/spi0_master.c:223: URXNIE = 1; // Enable RX interrupt. setb _URX0IE C$spi0_master.c$225$1$1 ==. ; libraries/src/spi_master/spi0_master.c:225: while (bytesLeft); 00101$: mov a,_bytesLeft orl a,(_bytesLeft + 1) jnz 00101$ C$spi0_master.c$226$1$1 ==. ; libraries/src/spi_master/spi0_master.c:226: return rxByte; mov dptr,#_spi0MasterSendByte_rxByte_1_1 movx a,@dptr C$spi0_master.c$227$1$1 ==. XG$spi0MasterSendByte$0$0 ==. mov dpl,a ret ;------------------------------------------------------------ ;Allocation info for local variables in function 'spi0MasterReceiveByte' ;------------------------------------------------------------ ;------------------------------------------------------------ G$spi0MasterReceiveByte$0$0 ==. C$spi0_master.c$229$1$1 ==. ; libraries/src/spi_master/spi0_master.c:229: uint8 spiNMasterReceiveByte(void) ; ----------------------------------------- ; function spi0MasterReceiveByte ; ----------------------------------------- _spi0MasterReceiveByte: C$spi0_master.c$231$1$1 ==. ; libraries/src/spi_master/spi0_master.c:231: return spiNMasterSendByte(0xFF); mov dpl,#0xFF C$spi0_master.c$232$1$1 ==. XG$spi0MasterReceiveByte$0$0 ==. ljmp _spi0MasterSendByte ;------------------------------------------------------------ ;Allocation info for local variables in function 'ISR_URX0' ;------------------------------------------------------------ ;------------------------------------------------------------ G$ISR_URX0$0$0 ==. C$spi0_master.c$234$1$1 ==. ; libraries/src/spi_master/spi0_master.c:234: ISR_URX() ; ----------------------------------------- ; function ISR_URX0 ; ----------------------------------------- _ISR_URX0: push acc push dpl push dph push psw mov psw,#0x00 C$spi0_master.c$236$1$1 ==. ; libraries/src/spi_master/spi0_master.c:236: URXNIF = 0; clr _URX0IF C$spi0_master.c$238$1$1 ==. ; libraries/src/spi_master/spi0_master.c:238: *rxPointer = UNDBUF; mov dpl,_rxPointer mov dph,(_rxPointer + 1) mov a,_U0DBUF movx @dptr,a C$spi0_master.c$239$1$1 ==. ; libraries/src/spi_master/spi0_master.c:239: rxPointer++; inc _rxPointer clr a cjne a,_rxPointer,00107$ inc (_rxPointer + 1) 00107$: C$spi0_master.c$240$1$1 ==. ; libraries/src/spi_master/spi0_master.c:240: bytesLeft--; dec _bytesLeft mov a,#0xff cjne a,_bytesLeft,00108$ dec (_bytesLeft + 1) 00108$: C$spi0_master.c$242$1$1 ==. ; libraries/src/spi_master/spi0_master.c:242: if (bytesLeft) mov a,_bytesLeft orl a,(_bytesLeft + 1) jz 00102$ C$spi0_master.c$244$2$2 ==. ; libraries/src/spi_master/spi0_master.c:244: txPointer++; inc _txPointer clr a cjne a,_txPointer,00110$ inc (_txPointer + 1) 00110$: C$spi0_master.c$245$2$2 ==. ; libraries/src/spi_master/spi0_master.c:245: UNDBUF = *txPointer; mov dpl,_txPointer mov dph,(_txPointer + 1) movx a,@dptr mov _U0DBUF,a sjmp 00104$ 00102$: C$spi0_master.c$249$2$3 ==. ; libraries/src/spi_master/spi0_master.c:249: URXNIE = 0; clr _URX0IE 00104$: pop psw pop dph pop dpl pop acc C$spi0_master.c$251$1$1 ==. XG$ISR_URX0$0$0 ==. reti ; eliminated unneeded push/pop b .area CSEG (CODE) .area CONST (CODE) .area XINIT (CODE) .area CABS (ABS,CODE)