M:i2c
F:G$i2cSetFrequency$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$i2cSetTimeout$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$i2cReadScl$0$0({2}DF,SB0$1:U),C,0,0,0,0,0
F:G$i2cReadSda$0$0({2}DF,SB0$1:U),C,0,0,0,0,0
F:G$i2cClearScl$0$0({2}DF,SV:S),C,0,0,0,0,0
F:G$i2cClearSda$0$0({2}DF,SV:S),C,0,0,0,0,0
F:G$i2cWaitForHighScl$0$0({2}DF,SV:S),C,0,0,0,0,0
F:G$i2cStop$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$i2cStart$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$i2cWriteBit$0$0({2}DF,SV:S),C,0,0,0,0,0
F:G$i2cReadBit$0$0({2}DF,SB0$1:U),C,0,0,0,0,0
F:G$i2cWriteByte$0$0({2}DF,SB0$1:U),Z,0,0,0,0,0
F:G$i2cReadByte$0$0({2}DF,SC:U),Z,0,0,0,0,0
T:Fi2c$__00010000[({0}S:S$SRCADDRH$0$0({1}SC:U),Z,0,0)({1}S:S$SRCADDRL$0$0({1}SC:U),Z,0,0)({2}S:S$DESTADDRH$0$0({1}SC:U),Z,0,0)({3}S:S$DESTADDRL$0$0({1}SC:U),Z,0,0)({4}S:S$VLEN_LENH$0$0({1}SC:U),Z,0,0)({5}S:S$LENL$0$0({1}SC:U),Z,0,0)({6}S:S$DC6$0$0({1}SC:U),Z,0,0)({7}S:S$DC7$0$0({1}SC:U),Z,0,0)]
F:G$i2cReadByte$0$0({2}DF,SC:U),Z,0,0,0,0,0
F:G$i2cReadByte$0$0({2}DF,SC:U),Z,0,0,0,0,0
F:G$i2cReadByte$0$0({2}DF,SC:U),Z,0,0,0,0,0
F:G$i2cReadByte$0$0({2}DF,SC:U),Z,0,0,0,0,0
F:G$i2cReadByte$0$0({2}DF,SC:U),Z,0,0,0,0,0
S:G$i2cPinScl$0$0({1}SC:U),E,0,0
S:G$i2cPinSda$0$0({1}SC:U),E,0,0
S:Li2cWaitForHighScl$sloc0$1$0({4}SL:U),E,0,0
S:Fi2c$started$0$0({1}SB0$1:U),H,0,0
S:G$i2cTimeoutOccurred$0$0({1}SB0$1:U),H,0,0
S:Fi2c$internalTimeoutOccurred$0$0({1}SB0$1:U),H,0,0
S:Li2cWriteBit$b$1$1({1}SB0$1:U),H,0,0
S:Li2cReadBit$b$1$1({1}SB0$1:U),H,0,0
S:Li2cWriteByte$nack$1$1({1}SB0$1:U),H,0,0
S:Li2cReadByte$nack$1$1({1}SB0$1:U),H,0,0
S:Li2cReadByte$b$1$1({1}SB0$1:U),H,0,0
S:Li2cSetFrequency$freqKHz$1$1({2}SI:U),R,0,0,[r2,r3]
S:Li2cSetTimeout$timeoutMs$1$1({2}SI:U),R,0,0,[]
S:Li2cWaitForHighScl$timeoutMs$1$1({2}SI:U),R,0,0,[r2,r3]
S:Li2cWaitForHighScl$time$1$1({4}SL:U),P,0,0
S:Li2cWriteByte$byte$1$1({1}SC:U),R,0,0,[r2]
S:Li2cWriteByte$i$1$1({1}SC:U),R,0,0,[r3]
S:Li2cReadByte$byte$1$1({2}SI:U),R,0,0,[r2,r3]
S:Li2cReadByte$i$1$1({1}SC:U),R,0,0,[r4]
S:Fi2c$SYNC1$0$0({1}SC:U),F,0,0
S:Fi2c$SYNC0$0$0({1}SC:U),F,0,0
S:Fi2c$PKTLEN$0$0({1}SC:U),F,0,0
S:Fi2c$PKTCTRL1$0$0({1}SC:U),F,0,0
S:Fi2c$PKTCTRL0$0$0({1}SC:U),F,0,0
S:Fi2c$ADDR$0$0({1}SC:U),F,0,0
S:Fi2c$CHANNR$0$0({1}SC:U),F,0,0
S:Fi2c$FSCTRL1$0$0({1}SC:U),F,0,0
S:Fi2c$FSCTRL0$0$0({1}SC:U),F,0,0
S:Fi2c$FREQ2$0$0({1}SC:U),F,0,0
S:Fi2c$FREQ1$0$0({1}SC:U),F,0,0
S:Fi2c$FREQ0$0$0({1}SC:U),F,0,0
S:Fi2c$MDMCFG4$0$0({1}SC:U),F,0,0
S:Fi2c$MDMCFG3$0$0({1}SC:U),F,0,0
S:Fi2c$MDMCFG2$0$0({1}SC:U),F,0,0
S:Fi2c$MDMCFG1$0$0({1}SC:U),F,0,0
S:Fi2c$MDMCFG0$0$0({1}SC:U),F,0,0
S:Fi2c$DEVIATN$0$0({1}SC:U),F,0,0
S:Fi2c$MCSM2$0$0({1}SC:U),F,0,0
S:Fi2c$MCSM1$0$0({1}SC:U),F,0,0
S:Fi2c$MCSM0$0$0({1}SC:U),F,0,0
S:Fi2c$FOCCFG$0$0({1}SC:U),F,0,0
S:Fi2c$BSCFG$0$0({1}SC:U),F,0,0
S:Fi2c$AGCCTRL2$0$0({1}SC:U),F,0,0
S:Fi2c$AGCCTRL1$0$0({1}SC:U),F,0,0
S:Fi2c$AGCCTRL0$0$0({1}SC:U),F,0,0
S:Fi2c$FREND1$0$0({1}SC:U),F,0,0
S:Fi2c$FREND0$0$0({1}SC:U),F,0,0
S:Fi2c$FSCAL3$0$0({1}SC:U),F,0,0
S:Fi2c$FSCAL2$0$0({1}SC:U),F,0,0
S:Fi2c$FSCAL1$0$0({1}SC:U),F,0,0
S:Fi2c$FSCAL0$0$0({1}SC:U),F,0,0
S:Fi2c$TEST2$0$0({1}SC:U),F,0,0
S:Fi2c$TEST1$0$0({1}SC:U),F,0,0
S:Fi2c$TEST0$0$0({1}SC:U),F,0,0
S:Fi2c$PA_TABLE0$0$0({1}SC:U),F,0,0
S:Fi2c$IOCFG2$0$0({1}SC:U),F,0,0
S:Fi2c$IOCFG1$0$0({1}SC:U),F,0,0
S:Fi2c$IOCFG0$0$0({1}SC:U),F,0,0
S:Fi2c$PARTNUM$0$0({1}SC:U),F,0,0
S:Fi2c$VERSION$0$0({1}SC:U),F,0,0
S:Fi2c$FREQEST$0$0({1}SC:U),F,0,0
S:Fi2c$LQI$0$0({1}SC:U),F,0,0
S:Fi2c$RSSI$0$0({1}SC:U),F,0,0
S:Fi2c$MARCSTATE$0$0({1}SC:U),F,0,0
S:Fi2c$PKTSTATUS$0$0({1}SC:U),F,0,0
S:Fi2c$VCO_VC_DAC$0$0({1}SC:U),F,0,0
S:Fi2c$I2SCFG0$0$0({1}SC:U),F,0,0
S:Fi2c$I2SCFG1$0$0({1}SC:U),F,0,0
S:Fi2c$I2SDATL$0$0({1}SC:U),F,0,0
S:Fi2c$I2SDATH$0$0({1}SC:U),F,0,0
S:Fi2c$I2SWCNT$0$0({1}SC:U),F,0,0
S:Fi2c$I2SSTAT$0$0({1}SC:U),F,0,0
S:Fi2c$I2SCLKF0$0$0({1}SC:U),F,0,0
S:Fi2c$I2SCLKF1$0$0({1}SC:U),F,0,0
S:Fi2c$I2SCLKF2$0$0({1}SC:U),F,0,0
S:Fi2c$USBADDR$0$0({1}SC:U),F,0,0
S:Fi2c$USBPOW$0$0({1}SC:U),F,0,0
S:Fi2c$USBIIF$0$0({1}SC:U),F,0,0
S:Fi2c$USBOIF$0$0({1}SC:U),F,0,0
S:Fi2c$USBCIF$0$0({1}SC:U),F,0,0
S:Fi2c$USBIIE$0$0({1}SC:U),F,0,0
S:Fi2c$USBOIE$0$0({1}SC:U),F,0,0
S:Fi2c$USBCIE$0$0({1}SC:U),F,0,0
S:Fi2c$USBFRML$0$0({1}SC:U),F,0,0
S:Fi2c$USBFRMH$0$0({1}SC:U),F,0,0
S:Fi2c$USBINDEX$0$0({1}SC:U),F,0,0
S:Fi2c$USBMAXI$0$0({1}SC:U),F,0,0
S:Fi2c$USBCSIL$0$0({1}SC:U),F,0,0
S:Fi2c$USBCSIH$0$0({1}SC:U),F,0,0
S:Fi2c$USBMAXO$0$0({1}SC:U),F,0,0
S:Fi2c$USBCSOL$0$0({1}SC:U),F,0,0
S:Fi2c$USBCSOH$0$0({1}SC:U),F,0,0
S:Fi2c$USBCNTL$0$0({1}SC:U),F,0,0
S:Fi2c$USBCNTH$0$0({1}SC:U),F,0,0
S:Fi2c$USBF0$0$0({1}SC:U),F,0,0
S:Fi2c$USBF1$0$0({1}SC:U),F,0,0
S:Fi2c$USBF2$0$0({1}SC:U),F,0,0
S:Fi2c$USBF3$0$0({1}SC:U),F,0,0
S:Fi2c$USBF4$0$0({1}SC:U),F,0,0
S:Fi2c$USBF5$0$0({1}SC:U),F,0,0
S:Fi2c$halfPeriodUs$0$0({2}SI:U),F,0,0
S:Fi2c$timeout$0$0({2}SI:U),F,0,0
S:Fi2c$P0$0$0({1}SC:U),I,0,0
S:Fi2c$SP$0$0({1}SC:U),I,0,0
S:Fi2c$DPL0$0$0({1}SC:U),I,0,0
S:Fi2c$DPH0$0$0({1}SC:U),I,0,0
S:Fi2c$DPL1$0$0({1}SC:U),I,0,0
S:Fi2c$DPH1$0$0({1}SC:U),I,0,0
S:Fi2c$U0CSR$0$0({1}SC:U),I,0,0
S:Fi2c$PCON$0$0({1}SC:U),I,0,0
S:Fi2c$TCON$0$0({1}SC:U),I,0,0
S:Fi2c$P0IFG$0$0({1}SC:U),I,0,0
S:Fi2c$P1IFG$0$0({1}SC:U),I,0,0
S:Fi2c$P2IFG$0$0({1}SC:U),I,0,0
S:Fi2c$PICTL$0$0({1}SC:U),I,0,0
S:Fi2c$P1IEN$0$0({1}SC:U),I,0,0
S:Fi2c$P0INP$0$0({1}SC:U),I,0,0
S:Fi2c$P1$0$0({1}SC:U),I,0,0
S:Fi2c$RFIM$0$0({1}SC:U),I,0,0
S:Fi2c$DPS$0$0({1}SC:U),I,0,0
S:Fi2c$MPAGE$0$0({1}SC:U),I,0,0
S:Fi2c$ENDIAN$0$0({1}SC:U),I,0,0
S:Fi2c$S0CON$0$0({1}SC:U),I,0,0
S:Fi2c$IEN2$0$0({1}SC:U),I,0,0
S:Fi2c$S1CON$0$0({1}SC:U),I,0,0
S:Fi2c$T2CT$0$0({1}SC:U),I,0,0
S:Fi2c$T2PR$0$0({1}SC:U),I,0,0
S:Fi2c$T2CTL$0$0({1}SC:U),I,0,0
S:Fi2c$P2$0$0({1}SC:U),I,0,0
S:Fi2c$WORIRQ$0$0({1}SC:U),I,0,0
S:Fi2c$WORCTRL$0$0({1}SC:U),I,0,0
S:Fi2c$WOREVT0$0$0({1}SC:U),I,0,0
S:Fi2c$WOREVT1$0$0({1}SC:U),I,0,0
S:Fi2c$WORTIME0$0$0({1}SC:U),I,0,0
S:Fi2c$WORTIME1$0$0({1}SC:U),I,0,0
S:Fi2c$IEN0$0$0({1}SC:U),I,0,0
S:Fi2c$IP0$0$0({1}SC:U),I,0,0
S:Fi2c$FWT$0$0({1}SC:U),I,0,0
S:Fi2c$FADDRL$0$0({1}SC:U),I,0,0
S:Fi2c$FADDRH$0$0({1}SC:U),I,0,0
S:Fi2c$FCTL$0$0({1}SC:U),I,0,0
S:Fi2c$FWDATA$0$0({1}SC:U),I,0,0
S:Fi2c$ENCDI$0$0({1}SC:U),I,0,0
S:Fi2c$ENCDO$0$0({1}SC:U),I,0,0
S:Fi2c$ENCCS$0$0({1}SC:U),I,0,0
S:Fi2c$ADCCON1$0$0({1}SC:U),I,0,0
S:Fi2c$ADCCON2$0$0({1}SC:U),I,0,0
S:Fi2c$ADCCON3$0$0({1}SC:U),I,0,0
S:Fi2c$IEN1$0$0({1}SC:U),I,0,0
S:Fi2c$IP1$0$0({1}SC:U),I,0,0
S:Fi2c$ADCL$0$0({1}SC:U),I,0,0
S:Fi2c$ADCH$0$0({1}SC:U),I,0,0
S:Fi2c$RNDL$0$0({1}SC:U),I,0,0
S:Fi2c$RNDH$0$0({1}SC:U),I,0,0
S:Fi2c$SLEEP$0$0({1}SC:U),I,0,0
S:Fi2c$IRCON$0$0({1}SC:U),I,0,0
S:Fi2c$U0DBUF$0$0({1}SC:U),I,0,0
S:Fi2c$U0BAUD$0$0({1}SC:U),I,0,0
S:Fi2c$U0UCR$0$0({1}SC:U),I,0,0
S:Fi2c$U0GCR$0$0({1}SC:U),I,0,0
S:Fi2c$CLKCON$0$0({1}SC:U),I,0,0
S:Fi2c$MEMCTR$0$0({1}SC:U),I,0,0
S:Fi2c$WDCTL$0$0({1}SC:U),I,0,0
S:Fi2c$T3CNT$0$0({1}SC:U),I,0,0
S:Fi2c$T3CTL$0$0({1}SC:U),I,0,0
S:Fi2c$T3CCTL0$0$0({1}SC:U),I,0,0
S:Fi2c$T3CC0$0$0({1}SC:U),I,0,0
S:Fi2c$T3CCTL1$0$0({1}SC:U),I,0,0
S:Fi2c$T3CC1$0$0({1}SC:U),I,0,0
S:Fi2c$PSW$0$0({1}SC:U),I,0,0
S:Fi2c$DMAIRQ$0$0({1}SC:U),I,0,0
S:Fi2c$DMA1CFGL$0$0({1}SC:U),I,0,0
S:Fi2c$DMA1CFGH$0$0({1}SC:U),I,0,0
S:Fi2c$DMA0CFGL$0$0({1}SC:U),I,0,0
S:Fi2c$DMA0CFGH$0$0({1}SC:U),I,0,0
S:Fi2c$DMAARM$0$0({1}SC:U),I,0,0
S:Fi2c$DMAREQ$0$0({1}SC:U),I,0,0
S:Fi2c$TIMIF$0$0({1}SC:U),I,0,0
S:Fi2c$RFD$0$0({1}SC:U),I,0,0
S:Fi2c$T1CC0L$0$0({1}SC:U),I,0,0
S:Fi2c$T1CC0H$0$0({1}SC:U),I,0,0
S:Fi2c$T1CC1L$0$0({1}SC:U),I,0,0
S:Fi2c$T1CC1H$0$0({1}SC:U),I,0,0
S:Fi2c$T1CC2L$0$0({1}SC:U),I,0,0
S:Fi2c$T1CC2H$0$0({1}SC:U),I,0,0
S:Fi2c$ACC$0$0({1}SC:U),I,0,0
S:Fi2c$RFST$0$0({1}SC:U),I,0,0
S:Fi2c$T1CNTL$0$0({1}SC:U),I,0,0
S:Fi2c$T1CNTH$0$0({1}SC:U),I,0,0
S:Fi2c$T1CTL$0$0({1}SC:U),I,0,0
S:Fi2c$T1CCTL0$0$0({1}SC:U),I,0,0
S:Fi2c$T1CCTL1$0$0({1}SC:U),I,0,0
S:Fi2c$T1CCTL2$0$0({1}SC:U),I,0,0
S:Fi2c$IRCON2$0$0({1}SC:U),I,0,0
S:Fi2c$RFIF$0$0({1}SC:U),I,0,0
S:Fi2c$T4CNT$0$0({1}SC:U),I,0,0
S:Fi2c$T4CTL$0$0({1}SC:U),I,0,0
S:Fi2c$T4CCTL0$0$0({1}SC:U),I,0,0
S:Fi2c$T4CC0$0$0({1}SC:U),I,0,0
S:Fi2c$T4CCTL1$0$0({1}SC:U),I,0,0
S:Fi2c$T4CC1$0$0({1}SC:U),I,0,0
S:Fi2c$B$0$0({1}SC:U),I,0,0
S:Fi2c$PERCFG$0$0({1}SC:U),I,0,0
S:Fi2c$ADCCFG$0$0({1}SC:U),I,0,0
S:Fi2c$P0SEL$0$0({1}SC:U),I,0,0
S:Fi2c$P1SEL$0$0({1}SC:U),I,0,0
S:Fi2c$P2SEL$0$0({1}SC:U),I,0,0
S:Fi2c$P1INP$0$0({1}SC:U),I,0,0
S:Fi2c$P2INP$0$0({1}SC:U),I,0,0
S:Fi2c$U1CSR$0$0({1}SC:U),I,0,0
S:Fi2c$U1DBUF$0$0({1}SC:U),I,0,0
S:Fi2c$U1BAUD$0$0({1}SC:U),I,0,0
S:Fi2c$U1UCR$0$0({1}SC:U),I,0,0
S:Fi2c$U1GCR$0$0({1}SC:U),I,0,0
S:Fi2c$P0DIR$0$0({1}SC:U),I,0,0
S:Fi2c$P1DIR$0$0({1}SC:U),I,0,0
S:Fi2c$P2DIR$0$0({1}SC:U),I,0,0
S:Fi2c$DMA0CFG$0$0({2}SI:U),I,0,0
S:Fi2c$DMA1CFG$0$0({2}SI:U),I,0,0
S:Fi2c$FADDR$0$0({2}SI:U),I,0,0
S:Fi2c$ADC$0$0({2}SI:U),I,0,0
S:Fi2c$T1CC0$0$0({2}SI:U),I,0,0
S:Fi2c$T1CC1$0$0({2}SI:U),I,0,0
S:Fi2c$T1CC2$0$0({2}SI:U),I,0,0
S:Fi2c$P0_0$0$0({1}SX:U),J,0,0
S:Fi2c$P0_1$0$0({1}SX:U),J,0,0
S:Fi2c$P0_2$0$0({1}SX:U),J,0,0
S:Fi2c$P0_3$0$0({1}SX:U),J,0,0
S:Fi2c$P0_4$0$0({1}SX:U),J,0,0
S:Fi2c$P0_5$0$0({1}SX:U),J,0,0
S:Fi2c$P0_6$0$0({1}SX:U),J,0,0
S:Fi2c$P0_7$0$0({1}SX:U),J,0,0
S:Fi2c$_TCON_0$0$0({1}SX:U),J,0,0
S:Fi2c$RFTXRXIF$0$0({1}SX:U),J,0,0
S:Fi2c$_TCON_2$0$0({1}SX:U),J,0,0
S:Fi2c$URX0IF$0$0({1}SX:U),J,0,0
S:Fi2c$_TCON_4$0$0({1}SX:U),J,0,0
S:Fi2c$ADCIF$0$0({1}SX:U),J,0,0
S:Fi2c$_TCON_6$0$0({1}SX:U),J,0,0
S:Fi2c$URX1IF$0$0({1}SX:U),J,0,0
S:Fi2c$P1_0$0$0({1}SX:U),J,0,0
S:Fi2c$P1_1$0$0({1}SX:U),J,0,0
S:Fi2c$P1_2$0$0({1}SX:U),J,0,0
S:Fi2c$P1_3$0$0({1}SX:U),J,0,0
S:Fi2c$P1_4$0$0({1}SX:U),J,0,0
S:Fi2c$P1_5$0$0({1}SX:U),J,0,0
S:Fi2c$P1_6$0$0({1}SX:U),J,0,0
S:Fi2c$P1_7$0$0({1}SX:U),J,0,0
S:Fi2c$ENCIF_0$0$0({1}SX:U),J,0,0
S:Fi2c$ENCIF_1$0$0({1}SX:U),J,0,0
S:Fi2c$_SOCON2$0$0({1}SX:U),J,0,0
S:Fi2c$_SOCON3$0$0({1}SX:U),J,0,0
S:Fi2c$_SOCON4$0$0({1}SX:U),J,0,0
S:Fi2c$_SOCON5$0$0({1}SX:U),J,0,0
S:Fi2c$_SOCON6$0$0({1}SX:U),J,0,0
S:Fi2c$_SOCON7$0$0({1}SX:U),J,0,0
S:Fi2c$P2_0$0$0({1}SX:U),J,0,0
S:Fi2c$P2_1$0$0({1}SX:U),J,0,0
S:Fi2c$P2_2$0$0({1}SX:U),J,0,0
S:Fi2c$P2_3$0$0({1}SX:U),J,0,0
S:Fi2c$P2_4$0$0({1}SX:U),J,0,0
S:Fi2c$P2_5$0$0({1}SX:U),J,0,0
S:Fi2c$P2_6$0$0({1}SX:U),J,0,0
S:Fi2c$P2_7$0$0({1}SX:U),J,0,0
S:Fi2c$RFTXRXIE$0$0({1}SX:U),J,0,0
S:Fi2c$ADCIE$0$0({1}SX:U),J,0,0
S:Fi2c$URX0IE$0$0({1}SX:U),J,0,0
S:Fi2c$URX1IE$0$0({1}SX:U),J,0,0
S:Fi2c$ENCIE$0$0({1}SX:U),J,0,0
S:Fi2c$STIE$0$0({1}SX:U),J,0,0
S:Fi2c$_IEN06$0$0({1}SX:U),J,0,0
S:Fi2c$EA$0$0({1}SX:U),J,0,0
S:Fi2c$DMAIE$0$0({1}SX:U),J,0,0
S:Fi2c$T1IE$0$0({1}SX:U),J,0,0
S:Fi2c$T2IE$0$0({1}SX:U),J,0,0
S:Fi2c$T3IE$0$0({1}SX:U),J,0,0
S:Fi2c$T4IE$0$0({1}SX:U),J,0,0
S:Fi2c$P0IE$0$0({1}SX:U),J,0,0
S:Fi2c$_IEN16$0$0({1}SX:U),J,0,0
S:Fi2c$_IEN17$0$0({1}SX:U),J,0,0
S:Fi2c$DMAIF$0$0({1}SX:U),J,0,0
S:Fi2c$T1IF$0$0({1}SX:U),J,0,0
S:Fi2c$T2IF$0$0({1}SX:U),J,0,0
S:Fi2c$T3IF$0$0({1}SX:U),J,0,0
S:Fi2c$T4IF$0$0({1}SX:U),J,0,0
S:Fi2c$P0IF$0$0({1}SX:U),J,0,0
S:Fi2c$_IRCON6$0$0({1}SX:U),J,0,0
S:Fi2c$STIF$0$0({1}SX:U),J,0,0
S:Fi2c$P$0$0({1}SX:U),J,0,0
S:Fi2c$F1$0$0({1}SX:U),J,0,0
S:Fi2c$OV$0$0({1}SX:U),J,0,0
S:Fi2c$RS0$0$0({1}SX:U),J,0,0
S:Fi2c$RS1$0$0({1}SX:U),J,0,0
S:Fi2c$F0$0$0({1}SX:U),J,0,0
S:Fi2c$AC$0$0({1}SX:U),J,0,0
S:Fi2c$CY$0$0({1}SX:U),J,0,0
S:Fi2c$T3OVFIF$0$0({1}SX:U),J,0,0
S:Fi2c$T3CH0IF$0$0({1}SX:U),J,0,0
S:Fi2c$T3CH1IF$0$0({1}SX:U),J,0,0
S:Fi2c$T4OVFIF$0$0({1}SX:U),J,0,0
S:Fi2c$T4CH0IF$0$0({1}SX:U),J,0,0
S:Fi2c$T4CH1IF$0$0({1}SX:U),J,0,0
S:Fi2c$OVFIM$0$0({1}SX:U),J,0,0
S:Fi2c$_TIMIF7$0$0({1}SX:U),J,0,0
S:Fi2c$ACC_0$0$0({1}SX:U),J,0,0
S:Fi2c$ACC_1$0$0({1}SX:U),J,0,0
S:Fi2c$ACC_2$0$0({1}SX:U),J,0,0
S:Fi2c$ACC_3$0$0({1}SX:U),J,0,0
S:Fi2c$ACC_4$0$0({1}SX:U),J,0,0
S:Fi2c$ACC_5$0$0({1}SX:U),J,0,0
S:Fi2c$ACC_6$0$0({1}SX:U),J,0,0
S:Fi2c$ACC_7$0$0({1}SX:U),J,0,0
S:Fi2c$P2IF$0$0({1}SX:U),J,0,0
S:Fi2c$UTX0IF$0$0({1}SX:U),J,0,0
S:Fi2c$UTX1IF$0$0({1}SX:U),J,0,0
S:Fi2c$P1IF$0$0({1}SX:U),J,0,0
S:Fi2c$WDTIF$0$0({1}SX:U),J,0,0
S:Fi2c$_IRCON25$0$0({1}SX:U),J,0,0
S:Fi2c$_IRCON26$0$0({1}SX:U),J,0,0
S:Fi2c$_IRCON27$0$0({1}SX:U),J,0,0
S:Fi2c$B_0$0$0({1}SX:U),J,0,0
S:Fi2c$B_1$0$0({1}SX:U),J,0,0
S:Fi2c$B_2$0$0({1}SX:U),J,0,0
S:Fi2c$B_3$0$0({1}SX:U),J,0,0
S:Fi2c$B_4$0$0({1}SX:U),J,0,0
S:Fi2c$B_5$0$0({1}SX:U),J,0,0
S:Fi2c$B_6$0$0({1}SX:U),J,0,0
S:Fi2c$B_7$0$0({1}SX:U),J,0,0
S:Fi2c$U1ACTIVE$0$0({1}SX:U),J,0,0
S:Fi2c$U1TX_BYTE$0$0({1}SX:U),J,0,0
S:Fi2c$U1RX_BYTE$0$0({1}SX:U),J,0,0
S:Fi2c$U1ERR$0$0({1}SX:U),J,0,0
S:Fi2c$U1FE$0$0({1}SX:U),J,0,0
S:Fi2c$U1SLAVE$0$0({1}SX:U),J,0,0
S:Fi2c$U1RE$0$0({1}SX:U),J,0,0
S:Fi2c$U1MODE$0$0({1}SX:U),J,0,0
S:G$systemInit$0$0({2}DF,SV:S),C,0,0
S:G$boardIoInit$0$0({2}DF,SV:S),C,0,0
S:G$boardClockInit$0$0({2}DF,SV:S),C,0,0
S:G$boardService$0$0({2}DF,SV:S),C,0,0
S:G$boardStartBootloaderIfNeeded$0$0({2}DF,SV:S),C,0,0
S:G$boardStartBootloader$0$0({2}DF,SV:S),C,0,0
S:G$usbPowerPresent$0$0({2}DF,SB0$1:U),C,0,0
S:G$vinPowerPresent$0$0({2}DF,SB0$1:U),C,0,0
S:G$enableUsbPullup$0$0({2}DF,SV:S),C,0,0
S:G$disableUsbPullup$0$0({2}DF,SV:S),C,0,0
S:G$timeInit$0$0({2}DF,SV:S),C,0,0
S:G$getMs$0$0({2}DF,SL:U),C,0,0
S:G$ISR_T4$0$0({2}DF,SV:S),C,0,0
S:G$delayMicroseconds$0$0({2}DF,SV:S),C,0,0
S:G$delayMs$0$0({2}DF,SV:S),C,0,0
S:G$setDigitalOutput$0$0({2}DF,SV:S),C,0,0
S:G$setDigitalInput$0$0({2}DF,SV:S),C,0,0
S:G$isPinHigh$0$0({2}DF,SB0$1:U),C,0,0
S:G$setPort0PullType$0$0({2}DF,SV:S),C,0,0
S:G$setPort1PullType$0$0({2}DF,SV:S),C,0,0
S:G$setPort2PullType$0$0({2}DF,SV:S),C,0,0
S:G$i2cReadScl$0$0({2}DF,SB0$1:U),C,0,0
S:G$i2cReadSda$0$0({2}DF,SB0$1:U),C,0,0
S:G$i2cClearScl$0$0({2}DF,SV:S),C,0,0
S:G$i2cClearSda$0$0({2}DF,SV:S),C,0,0
S:G$i2cWaitForHighScl$0$0({2}DF,SV:S),C,0,0
S:G$i2cWriteBit$0$0({2}DF,SV:S),C,0,0
S:G$i2cReadBit$0$0({2}DF,SB0$1:U),C,0,0
S:G$serialNumber$0$0({4}DA4,SC:U),D,0,0
S:G$serialNumberStringDescriptor$0$0({0}DA0,SI:U),D,0,0
S:Fi2c$__xinit_halfPeriodUs$0$0({2}SI:U),C,0,0
S:Fi2c$__xinit_timeout$0$0({2}SI:U),C,0,0