M:adc
F:G$adcRead$0$0({2}DF,SI:U),Z,0,0,0,0,0
F:G$adcReadDifferential$0$0({2}DF,SI:S),Z,0,0,0,0,0
T:Fadc$__00010000[({0}S:S$SRCADDRH$0$0({1}SC:U),Z,0,0)({1}S:S$SRCADDRL$0$0({1}SC:U),Z,0,0)({2}S:S$DESTADDRH$0$0({1}SC:U),Z,0,0)({3}S:S$DESTADDRL$0$0({1}SC:U),Z,0,0)({4}S:S$VLEN_LENH$0$0({1}SC:U),Z,0,0)({5}S:S$LENL$0$0({1}SC:U),Z,0,0)({6}S:S$DC6$0$0({1}SC:U),Z,0,0)({7}S:S$DC7$0$0({1}SC:U),Z,0,0)]
S:LadcRead$channel$1$1({1}SC:U),R,0,0,[r2]
S:LadcReadDifferential$channel$1$1({1}SC:U),R,0,0,[r2]
S:Fadc$SYNC1$0$0({1}SC:U),F,0,0
S:Fadc$SYNC0$0$0({1}SC:U),F,0,0
S:Fadc$PKTLEN$0$0({1}SC:U),F,0,0
S:Fadc$PKTCTRL1$0$0({1}SC:U),F,0,0
S:Fadc$PKTCTRL0$0$0({1}SC:U),F,0,0
S:Fadc$ADDR$0$0({1}SC:U),F,0,0
S:Fadc$CHANNR$0$0({1}SC:U),F,0,0
S:Fadc$FSCTRL1$0$0({1}SC:U),F,0,0
S:Fadc$FSCTRL0$0$0({1}SC:U),F,0,0
S:Fadc$FREQ2$0$0({1}SC:U),F,0,0
S:Fadc$FREQ1$0$0({1}SC:U),F,0,0
S:Fadc$FREQ0$0$0({1}SC:U),F,0,0
S:Fadc$MDMCFG4$0$0({1}SC:U),F,0,0
S:Fadc$MDMCFG3$0$0({1}SC:U),F,0,0
S:Fadc$MDMCFG2$0$0({1}SC:U),F,0,0
S:Fadc$MDMCFG1$0$0({1}SC:U),F,0,0
S:Fadc$MDMCFG0$0$0({1}SC:U),F,0,0
S:Fadc$DEVIATN$0$0({1}SC:U),F,0,0
S:Fadc$MCSM2$0$0({1}SC:U),F,0,0
S:Fadc$MCSM1$0$0({1}SC:U),F,0,0
S:Fadc$MCSM0$0$0({1}SC:U),F,0,0
S:Fadc$FOCCFG$0$0({1}SC:U),F,0,0
S:Fadc$BSCFG$0$0({1}SC:U),F,0,0
S:Fadc$AGCCTRL2$0$0({1}SC:U),F,0,0
S:Fadc$AGCCTRL1$0$0({1}SC:U),F,0,0
S:Fadc$AGCCTRL0$0$0({1}SC:U),F,0,0
S:Fadc$FREND1$0$0({1}SC:U),F,0,0
S:Fadc$FREND0$0$0({1}SC:U),F,0,0
S:Fadc$FSCAL3$0$0({1}SC:U),F,0,0
S:Fadc$FSCAL2$0$0({1}SC:U),F,0,0
S:Fadc$FSCAL1$0$0({1}SC:U),F,0,0
S:Fadc$FSCAL0$0$0({1}SC:U),F,0,0
S:Fadc$TEST2$0$0({1}SC:U),F,0,0
S:Fadc$TEST1$0$0({1}SC:U),F,0,0
S:Fadc$TEST0$0$0({1}SC:U),F,0,0
S:Fadc$PA_TABLE0$0$0({1}SC:U),F,0,0
S:Fadc$IOCFG2$0$0({1}SC:U),F,0,0
S:Fadc$IOCFG1$0$0({1}SC:U),F,0,0
S:Fadc$IOCFG0$0$0({1}SC:U),F,0,0
S:Fadc$PARTNUM$0$0({1}SC:U),F,0,0
S:Fadc$VERSION$0$0({1}SC:U),F,0,0
S:Fadc$FREQEST$0$0({1}SC:U),F,0,0
S:Fadc$LQI$0$0({1}SC:U),F,0,0
S:Fadc$RSSI$0$0({1}SC:U),F,0,0
S:Fadc$MARCSTATE$0$0({1}SC:U),F,0,0
S:Fadc$PKTSTATUS$0$0({1}SC:U),F,0,0
S:Fadc$VCO_VC_DAC$0$0({1}SC:U),F,0,0
S:Fadc$I2SCFG0$0$0({1}SC:U),F,0,0
S:Fadc$I2SCFG1$0$0({1}SC:U),F,0,0
S:Fadc$I2SDATL$0$0({1}SC:U),F,0,0
S:Fadc$I2SDATH$0$0({1}SC:U),F,0,0
S:Fadc$I2SWCNT$0$0({1}SC:U),F,0,0
S:Fadc$I2SSTAT$0$0({1}SC:U),F,0,0
S:Fadc$I2SCLKF0$0$0({1}SC:U),F,0,0
S:Fadc$I2SCLKF1$0$0({1}SC:U),F,0,0
S:Fadc$I2SCLKF2$0$0({1}SC:U),F,0,0
S:Fadc$USBADDR$0$0({1}SC:U),F,0,0
S:Fadc$USBPOW$0$0({1}SC:U),F,0,0
S:Fadc$USBIIF$0$0({1}SC:U),F,0,0
S:Fadc$USBOIF$0$0({1}SC:U),F,0,0
S:Fadc$USBCIF$0$0({1}SC:U),F,0,0
S:Fadc$USBIIE$0$0({1}SC:U),F,0,0
S:Fadc$USBOIE$0$0({1}SC:U),F,0,0
S:Fadc$USBCIE$0$0({1}SC:U),F,0,0
S:Fadc$USBFRML$0$0({1}SC:U),F,0,0
S:Fadc$USBFRMH$0$0({1}SC:U),F,0,0
S:Fadc$USBINDEX$0$0({1}SC:U),F,0,0
S:Fadc$USBMAXI$0$0({1}SC:U),F,0,0
S:Fadc$USBCSIL$0$0({1}SC:U),F,0,0
S:Fadc$USBCSIH$0$0({1}SC:U),F,0,0
S:Fadc$USBMAXO$0$0({1}SC:U),F,0,0
S:Fadc$USBCSOL$0$0({1}SC:U),F,0,0
S:Fadc$USBCSOH$0$0({1}SC:U),F,0,0
S:Fadc$USBCNTL$0$0({1}SC:U),F,0,0
S:Fadc$USBCNTH$0$0({1}SC:U),F,0,0
S:Fadc$USBF0$0$0({1}SC:U),F,0,0
S:Fadc$USBF1$0$0({1}SC:U),F,0,0
S:Fadc$USBF2$0$0({1}SC:U),F,0,0
S:Fadc$USBF3$0$0({1}SC:U),F,0,0
S:Fadc$USBF4$0$0({1}SC:U),F,0,0
S:Fadc$USBF5$0$0({1}SC:U),F,0,0
S:Fadc$P0$0$0({1}SC:U),I,0,0
S:Fadc$SP$0$0({1}SC:U),I,0,0
S:Fadc$DPL0$0$0({1}SC:U),I,0,0
S:Fadc$DPH0$0$0({1}SC:U),I,0,0
S:Fadc$DPL1$0$0({1}SC:U),I,0,0
S:Fadc$DPH1$0$0({1}SC:U),I,0,0
S:Fadc$U0CSR$0$0({1}SC:U),I,0,0
S:Fadc$PCON$0$0({1}SC:U),I,0,0
S:Fadc$TCON$0$0({1}SC:U),I,0,0
S:Fadc$P0IFG$0$0({1}SC:U),I,0,0
S:Fadc$P1IFG$0$0({1}SC:U),I,0,0
S:Fadc$P2IFG$0$0({1}SC:U),I,0,0
S:Fadc$PICTL$0$0({1}SC:U),I,0,0
S:Fadc$P1IEN$0$0({1}SC:U),I,0,0
S:Fadc$P0INP$0$0({1}SC:U),I,0,0
S:Fadc$P1$0$0({1}SC:U),I,0,0
S:Fadc$RFIM$0$0({1}SC:U),I,0,0
S:Fadc$DPS$0$0({1}SC:U),I,0,0
S:Fadc$MPAGE$0$0({1}SC:U),I,0,0
S:Fadc$ENDIAN$0$0({1}SC:U),I,0,0
S:Fadc$S0CON$0$0({1}SC:U),I,0,0
S:Fadc$IEN2$0$0({1}SC:U),I,0,0
S:Fadc$S1CON$0$0({1}SC:U),I,0,0
S:Fadc$T2CT$0$0({1}SC:U),I,0,0
S:Fadc$T2PR$0$0({1}SC:U),I,0,0
S:Fadc$T2CTL$0$0({1}SC:U),I,0,0
S:Fadc$P2$0$0({1}SC:U),I,0,0
S:Fadc$WORIRQ$0$0({1}SC:U),I,0,0
S:Fadc$WORCTRL$0$0({1}SC:U),I,0,0
S:Fadc$WOREVT0$0$0({1}SC:U),I,0,0
S:Fadc$WOREVT1$0$0({1}SC:U),I,0,0
S:Fadc$WORTIME0$0$0({1}SC:U),I,0,0
S:Fadc$WORTIME1$0$0({1}SC:U),I,0,0
S:Fadc$IEN0$0$0({1}SC:U),I,0,0
S:Fadc$IP0$0$0({1}SC:U),I,0,0
S:Fadc$FWT$0$0({1}SC:U),I,0,0
S:Fadc$FADDRL$0$0({1}SC:U),I,0,0
S:Fadc$FADDRH$0$0({1}SC:U),I,0,0
S:Fadc$FCTL$0$0({1}SC:U),I,0,0
S:Fadc$FWDATA$0$0({1}SC:U),I,0,0
S:Fadc$ENCDI$0$0({1}SC:U),I,0,0
S:Fadc$ENCDO$0$0({1}SC:U),I,0,0
S:Fadc$ENCCS$0$0({1}SC:U),I,0,0
S:Fadc$ADCCON1$0$0({1}SC:U),I,0,0
S:Fadc$ADCCON2$0$0({1}SC:U),I,0,0
S:Fadc$ADCCON3$0$0({1}SC:U),I,0,0
S:Fadc$IEN1$0$0({1}SC:U),I,0,0
S:Fadc$IP1$0$0({1}SC:U),I,0,0
S:Fadc$ADCL$0$0({1}SC:U),I,0,0
S:Fadc$ADCH$0$0({1}SC:U),I,0,0
S:Fadc$RNDL$0$0({1}SC:U),I,0,0
S:Fadc$RNDH$0$0({1}SC:U),I,0,0
S:Fadc$SLEEP$0$0({1}SC:U),I,0,0
S:Fadc$IRCON$0$0({1}SC:U),I,0,0
S:Fadc$U0DBUF$0$0({1}SC:U),I,0,0
S:Fadc$U0BAUD$0$0({1}SC:U),I,0,0
S:Fadc$U0UCR$0$0({1}SC:U),I,0,0
S:Fadc$U0GCR$0$0({1}SC:U),I,0,0
S:Fadc$CLKCON$0$0({1}SC:U),I,0,0
S:Fadc$MEMCTR$0$0({1}SC:U),I,0,0
S:Fadc$WDCTL$0$0({1}SC:U),I,0,0
S:Fadc$T3CNT$0$0({1}SC:U),I,0,0
S:Fadc$T3CTL$0$0({1}SC:U),I,0,0
S:Fadc$T3CCTL0$0$0({1}SC:U),I,0,0
S:Fadc$T3CC0$0$0({1}SC:U),I,0,0
S:Fadc$T3CCTL1$0$0({1}SC:U),I,0,0
S:Fadc$T3CC1$0$0({1}SC:U),I,0,0
S:Fadc$PSW$0$0({1}SC:U),I,0,0
S:Fadc$DMAIRQ$0$0({1}SC:U),I,0,0
S:Fadc$DMA1CFGL$0$0({1}SC:U),I,0,0
S:Fadc$DMA1CFGH$0$0({1}SC:U),I,0,0
S:Fadc$DMA0CFGL$0$0({1}SC:U),I,0,0
S:Fadc$DMA0CFGH$0$0({1}SC:U),I,0,0
S:Fadc$DMAARM$0$0({1}SC:U),I,0,0
S:Fadc$DMAREQ$0$0({1}SC:U),I,0,0
S:Fadc$TIMIF$0$0({1}SC:U),I,0,0
S:Fadc$RFD$0$0({1}SC:U),I,0,0
S:Fadc$T1CC0L$0$0({1}SC:U),I,0,0
S:Fadc$T1CC0H$0$0({1}SC:U),I,0,0
S:Fadc$T1CC1L$0$0({1}SC:U),I,0,0
S:Fadc$T1CC1H$0$0({1}SC:U),I,0,0
S:Fadc$T1CC2L$0$0({1}SC:U),I,0,0
S:Fadc$T1CC2H$0$0({1}SC:U),I,0,0
S:Fadc$ACC$0$0({1}SC:U),I,0,0
S:Fadc$RFST$0$0({1}SC:U),I,0,0
S:Fadc$T1CNTL$0$0({1}SC:U),I,0,0
S:Fadc$T1CNTH$0$0({1}SC:U),I,0,0
S:Fadc$T1CTL$0$0({1}SC:U),I,0,0
S:Fadc$T1CCTL0$0$0({1}SC:U),I,0,0
S:Fadc$T1CCTL1$0$0({1}SC:U),I,0,0
S:Fadc$T1CCTL2$0$0({1}SC:U),I,0,0
S:Fadc$IRCON2$0$0({1}SC:U),I,0,0
S:Fadc$RFIF$0$0({1}SC:U),I,0,0
S:Fadc$T4CNT$0$0({1}SC:U),I,0,0
S:Fadc$T4CTL$0$0({1}SC:U),I,0,0
S:Fadc$T4CCTL0$0$0({1}SC:U),I,0,0
S:Fadc$T4CC0$0$0({1}SC:U),I,0,0
S:Fadc$T4CCTL1$0$0({1}SC:U),I,0,0
S:Fadc$T4CC1$0$0({1}SC:U),I,0,0
S:Fadc$B$0$0({1}SC:U),I,0,0
S:Fadc$PERCFG$0$0({1}SC:U),I,0,0
S:Fadc$ADCCFG$0$0({1}SC:U),I,0,0
S:Fadc$P0SEL$0$0({1}SC:U),I,0,0
S:Fadc$P1SEL$0$0({1}SC:U),I,0,0
S:Fadc$P2SEL$0$0({1}SC:U),I,0,0
S:Fadc$P1INP$0$0({1}SC:U),I,0,0
S:Fadc$P2INP$0$0({1}SC:U),I,0,0
S:Fadc$U1CSR$0$0({1}SC:U),I,0,0
S:Fadc$U1DBUF$0$0({1}SC:U),I,0,0
S:Fadc$U1BAUD$0$0({1}SC:U),I,0,0
S:Fadc$U1UCR$0$0({1}SC:U),I,0,0
S:Fadc$U1GCR$0$0({1}SC:U),I,0,0
S:Fadc$P0DIR$0$0({1}SC:U),I,0,0
S:Fadc$P1DIR$0$0({1}SC:U),I,0,0
S:Fadc$P2DIR$0$0({1}SC:U),I,0,0
S:Fadc$DMA0CFG$0$0({2}SI:U),I,0,0
S:Fadc$DMA1CFG$0$0({2}SI:U),I,0,0
S:Fadc$FADDR$0$0({2}SI:U),I,0,0
S:Fadc$ADC$0$0({2}SI:U),I,0,0
S:Fadc$T1CC0$0$0({2}SI:U),I,0,0
S:Fadc$T1CC1$0$0({2}SI:U),I,0,0
S:Fadc$T1CC2$0$0({2}SI:U),I,0,0
S:Fadc$P0_0$0$0({1}SX:U),J,0,0
S:Fadc$P0_1$0$0({1}SX:U),J,0,0
S:Fadc$P0_2$0$0({1}SX:U),J,0,0
S:Fadc$P0_3$0$0({1}SX:U),J,0,0
S:Fadc$P0_4$0$0({1}SX:U),J,0,0
S:Fadc$P0_5$0$0({1}SX:U),J,0,0
S:Fadc$P0_6$0$0({1}SX:U),J,0,0
S:Fadc$P0_7$0$0({1}SX:U),J,0,0
S:Fadc$_TCON_0$0$0({1}SX:U),J,0,0
S:Fadc$RFTXRXIF$0$0({1}SX:U),J,0,0
S:Fadc$_TCON_2$0$0({1}SX:U),J,0,0
S:Fadc$URX0IF$0$0({1}SX:U),J,0,0
S:Fadc$_TCON_4$0$0({1}SX:U),J,0,0
S:Fadc$ADCIF$0$0({1}SX:U),J,0,0
S:Fadc$_TCON_6$0$0({1}SX:U),J,0,0
S:Fadc$URX1IF$0$0({1}SX:U),J,0,0
S:Fadc$P1_0$0$0({1}SX:U),J,0,0
S:Fadc$P1_1$0$0({1}SX:U),J,0,0
S:Fadc$P1_2$0$0({1}SX:U),J,0,0
S:Fadc$P1_3$0$0({1}SX:U),J,0,0
S:Fadc$P1_4$0$0({1}SX:U),J,0,0
S:Fadc$P1_5$0$0({1}SX:U),J,0,0
S:Fadc$P1_6$0$0({1}SX:U),J,0,0
S:Fadc$P1_7$0$0({1}SX:U),J,0,0
S:Fadc$ENCIF_0$0$0({1}SX:U),J,0,0
S:Fadc$ENCIF_1$0$0({1}SX:U),J,0,0
S:Fadc$_SOCON2$0$0({1}SX:U),J,0,0
S:Fadc$_SOCON3$0$0({1}SX:U),J,0,0
S:Fadc$_SOCON4$0$0({1}SX:U),J,0,0
S:Fadc$_SOCON5$0$0({1}SX:U),J,0,0
S:Fadc$_SOCON6$0$0({1}SX:U),J,0,0
S:Fadc$_SOCON7$0$0({1}SX:U),J,0,0
S:Fadc$P2_0$0$0({1}SX:U),J,0,0
S:Fadc$P2_1$0$0({1}SX:U),J,0,0
S:Fadc$P2_2$0$0({1}SX:U),J,0,0
S:Fadc$P2_3$0$0({1}SX:U),J,0,0
S:Fadc$P2_4$0$0({1}SX:U),J,0,0
S:Fadc$P2_5$0$0({1}SX:U),J,0,0
S:Fadc$P2_6$0$0({1}SX:U),J,0,0
S:Fadc$P2_7$0$0({1}SX:U),J,0,0
S:Fadc$RFTXRXIE$0$0({1}SX:U),J,0,0
S:Fadc$ADCIE$0$0({1}SX:U),J,0,0
S:Fadc$URX0IE$0$0({1}SX:U),J,0,0
S:Fadc$URX1IE$0$0({1}SX:U),J,0,0
S:Fadc$ENCIE$0$0({1}SX:U),J,0,0
S:Fadc$STIE$0$0({1}SX:U),J,0,0
S:Fadc$_IEN06$0$0({1}SX:U),J,0,0
S:Fadc$EA$0$0({1}SX:U),J,0,0
S:Fadc$DMAIE$0$0({1}SX:U),J,0,0
S:Fadc$T1IE$0$0({1}SX:U),J,0,0
S:Fadc$T2IE$0$0({1}SX:U),J,0,0
S:Fadc$T3IE$0$0({1}SX:U),J,0,0
S:Fadc$T4IE$0$0({1}SX:U),J,0,0
S:Fadc$P0IE$0$0({1}SX:U),J,0,0
S:Fadc$_IEN16$0$0({1}SX:U),J,0,0
S:Fadc$_IEN17$0$0({1}SX:U),J,0,0
S:Fadc$DMAIF$0$0({1}SX:U),J,0,0
S:Fadc$T1IF$0$0({1}SX:U),J,0,0
S:Fadc$T2IF$0$0({1}SX:U),J,0,0
S:Fadc$T3IF$0$0({1}SX:U),J,0,0
S:Fadc$T4IF$0$0({1}SX:U),J,0,0
S:Fadc$P0IF$0$0({1}SX:U),J,0,0
S:Fadc$_IRCON6$0$0({1}SX:U),J,0,0
S:Fadc$STIF$0$0({1}SX:U),J,0,0
S:Fadc$P$0$0({1}SX:U),J,0,0
S:Fadc$F1$0$0({1}SX:U),J,0,0
S:Fadc$OV$0$0({1}SX:U),J,0,0
S:Fadc$RS0$0$0({1}SX:U),J,0,0
S:Fadc$RS1$0$0({1}SX:U),J,0,0
S:Fadc$F0$0$0({1}SX:U),J,0,0
S:Fadc$AC$0$0({1}SX:U),J,0,0
S:Fadc$CY$0$0({1}SX:U),J,0,0
S:Fadc$T3OVFIF$0$0({1}SX:U),J,0,0
S:Fadc$T3CH0IF$0$0({1}SX:U),J,0,0
S:Fadc$T3CH1IF$0$0({1}SX:U),J,0,0
S:Fadc$T4OVFIF$0$0({1}SX:U),J,0,0
S:Fadc$T4CH0IF$0$0({1}SX:U),J,0,0
S:Fadc$T4CH1IF$0$0({1}SX:U),J,0,0
S:Fadc$OVFIM$0$0({1}SX:U),J,0,0
S:Fadc$_TIMIF7$0$0({1}SX:U),J,0,0
S:Fadc$ACC_0$0$0({1}SX:U),J,0,0
S:Fadc$ACC_1$0$0({1}SX:U),J,0,0
S:Fadc$ACC_2$0$0({1}SX:U),J,0,0
S:Fadc$ACC_3$0$0({1}SX:U),J,0,0
S:Fadc$ACC_4$0$0({1}SX:U),J,0,0
S:Fadc$ACC_5$0$0({1}SX:U),J,0,0
S:Fadc$ACC_6$0$0({1}SX:U),J,0,0
S:Fadc$ACC_7$0$0({1}SX:U),J,0,0
S:Fadc$P2IF$0$0({1}SX:U),J,0,0
S:Fadc$UTX0IF$0$0({1}SX:U),J,0,0
S:Fadc$UTX1IF$0$0({1}SX:U),J,0,0
S:Fadc$P1IF$0$0({1}SX:U),J,0,0
S:Fadc$WDTIF$0$0({1}SX:U),J,0,0
S:Fadc$_IRCON25$0$0({1}SX:U),J,0,0
S:Fadc$_IRCON26$0$0({1}SX:U),J,0,0
S:Fadc$_IRCON27$0$0({1}SX:U),J,0,0
S:Fadc$B_0$0$0({1}SX:U),J,0,0
S:Fadc$B_1$0$0({1}SX:U),J,0,0
S:Fadc$B_2$0$0({1}SX:U),J,0,0
S:Fadc$B_3$0$0({1}SX:U),J,0,0
S:Fadc$B_4$0$0({1}SX:U),J,0,0
S:Fadc$B_5$0$0({1}SX:U),J,0,0
S:Fadc$B_6$0$0({1}SX:U),J,0,0
S:Fadc$B_7$0$0({1}SX:U),J,0,0
S:Fadc$U1ACTIVE$0$0({1}SX:U),J,0,0
S:Fadc$U1TX_BYTE$0$0({1}SX:U),J,0,0
S:Fadc$U1RX_BYTE$0$0({1}SX:U),J,0,0
S:Fadc$U1ERR$0$0({1}SX:U),J,0,0
S:Fadc$U1FE$0$0({1}SX:U),J,0,0
S:Fadc$U1SLAVE$0$0({1}SX:U),J,0,0
S:Fadc$U1RE$0$0({1}SX:U),J,0,0
S:Fadc$U1MODE$0$0({1}SX:U),J,0,0
S:G$adcReadVddMillivolts$0$0({2}DF,SI:U),C,0,0
S:G$adcSetMillivoltCalibration$0$0({2}DF,SV:S),C,0,0
S:G$adcConvertToMillivolts$0$0({2}DF,SI:S),C,0,0