spi_test_two.elf: file format elf32-avr Sections: Idx Name Size VMA LMA File off Algn 0 .text 00000c5c 00000000 00000000 00000094 2**1 CONTENTS, ALLOC, LOAD, READONLY, CODE 1 .data 00000008 00802000 00000c5c 00000cf0 2**0 CONTENTS, ALLOC, LOAD, DATA 2 .bss 00000042 00802008 00802008 00000cf8 2**0 ALLOC 3 .debug_aranges 00000080 00000000 00000000 00000cf8 2**0 CONTENTS, READONLY, DEBUGGING 4 .debug_pubnames 0000057d 00000000 00000000 00000d78 2**0 CONTENTS, READONLY, DEBUGGING 5 .debug_info 00002ed0 00000000 00000000 000012f5 2**0 CONTENTS, READONLY, DEBUGGING 6 .debug_abbrev 0000080c 00000000 00000000 000041c5 2**0 CONTENTS, READONLY, DEBUGGING 7 .debug_line 00000e3a 00000000 00000000 000049d1 2**0 CONTENTS, READONLY, DEBUGGING 8 .debug_frame 00000370 00000000 00000000 0000580c 2**2 CONTENTS, READONLY, DEBUGGING 9 .debug_str 00001728 00000000 00000000 00005b7c 2**0 CONTENTS, READONLY, DEBUGGING 10 .debug_loc 00000774 00000000 00000000 000072a4 2**0 CONTENTS, READONLY, DEBUGGING 11 .debug_ranges 00000030 00000000 00000000 00007a18 2**0 CONTENTS, READONLY, DEBUGGING Disassembly of section .text: 00000000 <__vectors>: 0: 0c 94 fa 00 jmp 0x1f4 ; 0x1f4 <__ctors_end> 4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 10: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 14: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 18: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 20: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 24: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 28: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 2c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 30: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 34: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 38: 0c 94 f6 02 jmp 0x5ec ; 0x5ec <__vector_14> 3c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 40: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 44: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 48: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 4c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 50: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 54: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 58: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 5c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 60: 0c 94 d6 02 jmp 0x5ac ; 0x5ac <__vector_24> 64: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 68: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 6c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 70: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 74: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 78: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 7c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 80: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 84: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 88: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 8c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 90: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 94: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 98: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 9c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> a0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> a4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> a8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> ac: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> b0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> b4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> b8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> bc: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> c0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> c4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> c8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> cc: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> d0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> d4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> d8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> dc: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> e0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> e4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> e8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> ec: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> f0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> f4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> f8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> fc: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 100: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 104: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 108: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 10c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 110: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 114: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 118: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 11c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 120: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 124: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 128: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 12c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 130: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 134: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 138: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 13c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 140: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 144: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 148: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 14c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 150: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 154: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 158: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 15c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 160: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 164: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 168: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 16c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 170: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 174: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 178: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 17c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 180: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 184: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 188: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 18c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 190: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 194: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 198: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 19c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1a0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1a4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1a8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1ac: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1b0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1b4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1b8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1bc: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1c0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1c4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1c8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1cc: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1d0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1d4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1d8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1dc: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1e0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1e4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1e8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1ec: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1f0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 000001f4 <__ctors_end>: 1f4: 11 24 eor r1, r1 1f6: 1f be out 0x3f, r1 ; 63 1f8: cf ef ldi r28, 0xFF ; 255 1fa: df e3 ldi r29, 0x3F ; 63 1fc: de bf out 0x3e, r29 ; 62 1fe: cd bf out 0x3d, r28 ; 61 200: 00 e0 ldi r16, 0x00 ; 0 202: 0c bf out 0x3c, r16 ; 60 204: 18 be out 0x38, r1 ; 56 206: 19 be out 0x39, r1 ; 57 208: 1a be out 0x3a, r1 ; 58 20a: 1b be out 0x3b, r1 ; 59 0000020c <__do_copy_data>: 20c: 10 e2 ldi r17, 0x20 ; 32 20e: a0 e0 ldi r26, 0x00 ; 0 210: b0 e2 ldi r27, 0x20 ; 32 212: ec e5 ldi r30, 0x5C ; 92 214: fc e0 ldi r31, 0x0C ; 12 216: 00 e0 ldi r16, 0x00 ; 0 218: 0b bf out 0x3b, r16 ; 59 21a: 02 c0 rjmp .+4 ; 0x220 <__do_copy_data+0x14> 21c: 07 90 elpm r0, Z+ 21e: 0d 92 st X+, r0 220: a8 30 cpi r26, 0x08 ; 8 222: b1 07 cpc r27, r17 224: d9 f7 brne .-10 ; 0x21c <__do_copy_data+0x10> 226: 1b be out 0x3b, r1 ; 59 00000228 <__do_clear_bss>: 228: 10 e2 ldi r17, 0x20 ; 32 22a: a8 e0 ldi r26, 0x08 ; 8 22c: b0 e2 ldi r27, 0x20 ; 32 22e: 01 c0 rjmp .+2 ; 0x232 <.do_clear_bss_start> 00000230 <.do_clear_bss_loop>: 230: 1d 92 st X+, r1 00000232 <.do_clear_bss_start>: 232: aa 34 cpi r26, 0x4A ; 74 234: b1 07 cpc r27, r17 236: e1 f7 brne .-8 ; 0x230 <.do_clear_bss_loop> 238: 0e 94 5e 03 call 0x6bc ; 0x6bc
23c: 0c 94 2c 06 jmp 0xc58 ; 0xc58 <_exit> 00000240 <__bad_interrupt>: 240: 0c 94 00 00 jmp 0 ; 0x0 <__vectors> 00000244 : Set up Timer/Counter 0 to work from CPICLK/64 with period of 31500 (a frequency of about 1 Hz) and enable overflow interrupt note: Initializing this timere will instantiate a heartbeat by nature of the interrupt linked to it */ TCC0.PER = 31650; 244: e0 e0 ldi r30, 0x00 ; 0 246: f8 e0 ldi r31, 0x08 ; 8 248: 82 ea ldi r24, 0xA2 ; 162 24a: 9b e7 ldi r25, 0x7B ; 123 24c: 86 a3 std Z+38, r24 ; 0x26 24e: 97 a3 std Z+39, r25 ; 0x27 TCC0.CTRLA = (TCC0.CTRLA & ~TC0_CLKSEL_gm) | TC_CLKSEL_DIV1024_gc; 250: 80 81 ld r24, Z 252: 80 7f andi r24, 0xF0 ; 240 254: 87 60 ori r24, 0x07 ; 7 256: 80 83 st Z, r24 TCC0.INTCTRLA = (TCC0.INTCTRLA & ~TC0_OVFINTLVL_gm) | 258: 86 81 ldd r24, Z+6 ; 0x06 25a: 8c 7f andi r24, 0xFC ; 252 25c: 82 60 ori r24, 0x02 ; 2 25e: 86 83 std Z+6, r24 ; 0x06 TC_OVFINTLVL_MED_gc; PMIC.CTRL |= PMIC_MEDLVLEN_bm; 260: e0 ea ldi r30, 0xA0 ; 160 262: f0 e0 ldi r31, 0x00 ; 0 264: 82 81 ldd r24, Z+2 ; 0x02 266: 82 60 ori r24, 0x02 ; 2 268: 82 83 std Z+2, r24 ; 0x02 } 26a: 08 95 ret 0000026c : /* --------------------------------------------------------------- */ void Process_SPI(void){ /* If the spi interrupt is fired do things */ if (spi->int_flag ==1 ){ 26c: a0 91 02 20 lds r26, 0x2002 270: b0 91 03 20 lds r27, 0x2003 274: 8c 91 ld r24, X 276: 81 30 cpi r24, 0x01 ; 1 278: 09 f0 breq .+2 ; 0x27c 27a: b0 c0 rjmp .+352 ; 0x3dc uint8_t send_byte = 0x00; uint8_t receive_byte = 0x00; /* Transmit */ /* ------------------------------------------------------ */ if (spi->tx_flag == 0){ 27c: 12 96 adiw r26, 0x02 ; 2 27e: 8c 91 ld r24, X 280: 12 97 sbiw r26, 0x02 ; 2 282: 88 23 and r24, r24 284: 29 f4 brne .+10 ; 0x290 spi->tx_counter = 0; 286: 14 96 adiw r26, 0x04 ; 4 288: 1c 92 st X, r1 28a: 14 97 sbiw r26, 0x04 ; 4 28c: 20 e0 ldi r18, 0x00 ; 0 28e: 44 c0 rjmp .+136 ; 0x318 send_byte = 0x00; }else{ if (spi->tx_counter == (spi->tx_len+4)){ 290: 14 96 adiw r26, 0x04 ; 4 292: 2c 91 ld r18, X 294: 14 97 sbiw r26, 0x04 ; 4 296: 30 e0 ldi r19, 0x00 ; 0 298: 18 96 adiw r26, 0x08 ; 8 29a: 8c 91 ld r24, X 29c: 18 97 sbiw r26, 0x08 ; 8 29e: 90 e0 ldi r25, 0x00 ; 0 2a0: 04 96 adiw r24, 0x04 ; 4 2a2: 28 17 cp r18, r24 2a4: 39 07 cpc r19, r25 2a6: 19 f4 brne .+6 ; 0x2ae spi->tx_counter = 0; 2a8: 14 96 adiw r26, 0x04 ; 4 2aa: 1c 92 st X, r1 2ac: 14 97 sbiw r26, 0x04 ; 4 } if (spi->tx_counter == (spi->tx_len+3)){ 2ae: 14 96 adiw r26, 0x04 ; 4 2b0: 2c 91 ld r18, X 2b2: 14 97 sbiw r26, 0x04 ; 4 2b4: 30 e0 ldi r19, 0x00 ; 0 2b6: 18 96 adiw r26, 0x08 ; 8 2b8: 8c 91 ld r24, X 2ba: 18 97 sbiw r26, 0x08 ; 8 2bc: 90 e0 ldi r25, 0x00 ; 0 2be: 03 96 adiw r24, 0x03 ; 3 2c0: 28 17 cp r18, r24 2c2: 39 07 cpc r19, r25 2c4: 11 f0 breq .+4 ; 0x2ca 2c6: 20 e0 ldi r18, 0x00 ; 0 2c8: 04 c0 rjmp .+8 ; 0x2d2 send_byte = SPI_END_TOKEN; spi->tx_flag = 0; 2ca: 12 96 adiw r26, 0x02 ; 2 2cc: 1c 92 st X, r1 2ce: 12 97 sbiw r26, 0x02 ; 2 2d0: 24 e4 ldi r18, 0x44 ; 68 } if (spi->tx_counter<(spi->tx_len+3) && spi->tx_counter>0){ 2d2: 14 96 adiw r26, 0x04 ; 4 2d4: 3c 91 ld r19, X 2d6: 14 97 sbiw r26, 0x04 ; 4 2d8: e3 2f mov r30, r19 2da: f0 e0 ldi r31, 0x00 ; 0 2dc: 18 96 adiw r26, 0x08 ; 8 2de: 8c 91 ld r24, X 2e0: 18 97 sbiw r26, 0x08 ; 8 2e2: 90 e0 ldi r25, 0x00 ; 0 2e4: 02 96 adiw r24, 0x02 ; 2 2e6: 8e 17 cp r24, r30 2e8: 9f 07 cpc r25, r31 2ea: 4c f0 brlt .+18 ; 0x2fe 2ec: 33 23 and r19, r19 2ee: 39 f0 breq .+14 ; 0x2fe send_byte = spi->tx_buffer[(spi->tx_counter)-1]; 2f0: ea 0f add r30, r26 2f2: fb 1f adc r31, r27 2f4: 22 89 ldd r18, Z+18 ; 0x12 spi->tx_counter++; 2f6: 3f 5f subi r19, 0xFF ; 255 2f8: 14 96 adiw r26, 0x04 ; 4 2fa: 3c 93 st X, r19 2fc: 14 97 sbiw r26, 0x04 ; 4 } if (spi->tx_counter == 0){ 2fe: 14 96 adiw r26, 0x04 ; 4 300: 8c 91 ld r24, X 302: 14 97 sbiw r26, 0x04 ; 4 304: 88 23 and r24, r24 306: 41 f4 brne .+16 ; 0x318 send_byte = SPI_START_TOKEN | spi->tx_len; 308: 18 96 adiw r26, 0x08 ; 8 30a: 2c 91 ld r18, X 30c: 18 97 sbiw r26, 0x08 ; 8 30e: 20 6b ori r18, 0xB0 ; 176 spi->tx_counter++; 310: 81 e0 ldi r24, 0x01 ; 1 312: 14 96 adiw r26, 0x04 ; 4 314: 8c 93 st X, r24 316: 14 97 sbiw r26, 0x04 ; 4 /* ------------------------------------------------------ */ /* For PIC */ /*receive_byte = spi_xfer(send_byte);*/ /* For atxmega */ SPI_SlaveWriteByte(&spiSlaveC, send_byte); 318: e0 91 08 20 lds r30, 0x2008 31c: f0 91 09 20 lds r31, 0x2009 320: 23 83 std Z+3, r18 ; 0x03 receive_byte = SPI_SlaveReadByte(&spiSlaveC); 322: 43 81 ldd r20, Z+3 ; 0x03 /* ------------------------------------------------------ */ /* Receive */ if (spi->rx_counter == (spi->rx_len+4)){ 324: 13 96 adiw r26, 0x03 ; 3 326: 2c 91 ld r18, X 328: 13 97 sbiw r26, 0x03 ; 3 32a: 30 e0 ldi r19, 0x00 ; 0 32c: 17 96 adiw r26, 0x07 ; 7 32e: 8c 91 ld r24, X 330: 17 97 sbiw r26, 0x07 ; 7 332: 90 e0 ldi r25, 0x00 ; 0 334: 04 96 adiw r24, 0x04 ; 4 336: 28 17 cp r18, r24 338: 39 07 cpc r19, r25 33a: 19 f4 brne .+6 ; 0x342 spi->rx_counter = 0; 33c: 13 96 adiw r26, 0x03 ; 3 33e: 1c 92 st X, r1 340: 13 97 sbiw r26, 0x03 ; 3 } if (spi->rx_counter == (spi->rx_len+3)){ 342: 13 96 adiw r26, 0x03 ; 3 344: 2c 91 ld r18, X 346: 13 97 sbiw r26, 0x03 ; 3 348: 30 e0 ldi r19, 0x00 ; 0 34a: 17 96 adiw r26, 0x07 ; 7 34c: 8c 91 ld r24, X 34e: 17 97 sbiw r26, 0x07 ; 7 350: 90 e0 ldi r25, 0x00 ; 0 352: 03 96 adiw r24, 0x03 ; 3 354: 28 17 cp r18, r24 356: 39 07 cpc r19, r25 358: a9 f4 brne .+42 ; 0x384 if (receive_byte == SPI_END_TOKEN){ 35a: 44 34 cpi r20, 0x44 ; 68 35c: 81 f4 brne .+32 ; 0x37e PORTE.OUTTGL = PIN4_bm; 35e: 80 e1 ldi r24, 0x10 ; 16 360: e0 e8 ldi r30, 0x80 ; 128 362: f6 e0 ldi r31, 0x06 ; 6 364: 87 83 std Z+7, r24 ; 0x07 spi->rx_flag = 1; 366: 81 e0 ldi r24, 0x01 ; 1 368: 11 96 adiw r26, 0x01 ; 1 36a: 8c 93 st X, r24 36c: 11 97 sbiw r26, 0x01 ; 1 spi->rx_counter++; 36e: 13 96 adiw r26, 0x03 ; 3 370: 8c 91 ld r24, X 372: 13 97 sbiw r26, 0x03 ; 3 374: 8f 5f subi r24, 0xFF ; 255 376: 13 96 adiw r26, 0x03 ; 3 378: 8c 93 st X, r24 37a: 13 97 sbiw r26, 0x03 ; 3 37c: 03 c0 rjmp .+6 ; 0x384 }else{ spi->rx_counter = 0; 37e: 13 96 adiw r26, 0x03 ; 3 380: 1c 92 st X, r1 382: 13 97 sbiw r26, 0x03 ; 3 } } if (spi->rx_counter<(spi->rx_len+3) && spi->rx_counter>0){ 384: 13 96 adiw r26, 0x03 ; 3 386: 2c 91 ld r18, X 388: 13 97 sbiw r26, 0x03 ; 3 38a: e2 2f mov r30, r18 38c: f0 e0 ldi r31, 0x00 ; 0 38e: 17 96 adiw r26, 0x07 ; 7 390: 8c 91 ld r24, X 392: 17 97 sbiw r26, 0x07 ; 7 394: 90 e0 ldi r25, 0x00 ; 0 396: 02 96 adiw r24, 0x02 ; 2 398: 8e 17 cp r24, r30 39a: 9f 07 cpc r25, r31 39c: 4c f0 brlt .+18 ; 0x3b0 39e: 22 23 and r18, r18 3a0: 39 f0 breq .+14 ; 0x3b0 spi->rx_buffer[(spi->rx_counter)-1] = receive_byte; 3a2: ea 0f add r30, r26 3a4: fb 1f adc r31, r27 3a6: 40 87 std Z+8, r20 ; 0x08 spi->rx_counter++; 3a8: 2f 5f subi r18, 0xFF ; 255 3aa: 13 96 adiw r26, 0x03 ; 3 3ac: 2c 93 st X, r18 3ae: 13 97 sbiw r26, 0x03 ; 3 } if (spi->rx_counter == 0){ 3b0: 13 96 adiw r26, 0x03 ; 3 3b2: 8c 91 ld r24, X 3b4: 13 97 sbiw r26, 0x03 ; 3 3b6: 88 23 and r24, r24 3b8: 81 f4 brne .+32 ; 0x3da if ((receive_byte & 0b11110000) == SPI_START_TOKEN){ 3ba: 84 2f mov r24, r20 3bc: 80 7f andi r24, 0xF0 ; 240 3be: 80 3b cpi r24, 0xB0 ; 176 3c0: 49 f4 brne .+18 ; 0x3d4 spi->rx_len = (receive_byte & 0b00001111); 3c2: 4f 70 andi r20, 0x0F ; 15 3c4: 17 96 adiw r26, 0x07 ; 7 3c6: 4c 93 st X, r20 3c8: 17 97 sbiw r26, 0x07 ; 7 spi->rx_counter++; 3ca: 81 e0 ldi r24, 0x01 ; 1 3cc: 13 96 adiw r26, 0x03 ; 3 3ce: 8c 93 st X, r24 3d0: 13 97 sbiw r26, 0x03 ; 3 3d2: 03 c0 rjmp .+6 ; 0x3da }else{ spi->rx_counter = 0; 3d4: 13 96 adiw r26, 0x03 ; 3 3d6: 1c 92 st X, r1 3d8: 13 97 sbiw r26, 0x03 ; 3 } } /* ------------------------------------------------------ */ spi->int_flag = 0; 3da: 1c 92 st X, r1 3dc: 08 95 ret 000003de : } return; } /* --------------------------------------------------------------- */ void Process_Transmit_Buffers(void){ 3de: cf 93 push r28 3e0: df 93 push r29 /* Priority is currently determined by the sequence of buffers in this function */ if (RB->tx_flag == 1){ 3e2: 20 91 04 20 lds r18, 0x2004 3e6: 30 91 05 20 lds r19, 0x2005 3ea: f9 01 movw r30, r18 3ec: 83 85 ldd r24, Z+11 ; 0x0b 3ee: 81 30 cpi r24, 0x01 ; 1 3f0: c9 f4 brne .+50 ; 0x424 spi->tx_len = RB->len; 3f2: c0 91 02 20 lds r28, 0x2002 3f6: d0 91 03 20 lds r29, 0x2003 3fa: 82 85 ldd r24, Z+10 ; 0x0a 3fc: 88 87 std Y+8, r24 ; 0x08 3fe: 40 e0 ldi r20, 0x00 ; 0 400: 08 c0 rjmp .+16 ; 0x412 for (uint8_t i=0;i<(spi->tx_len+2);i++){ spi->tx_buffer[i] = RB->buffer[i]; 402: fe 01 movw r30, r28 404: ea 0f add r30, r26 406: fb 1f adc r31, r27 408: a2 0f add r26, r18 40a: b3 1f adc r27, r19 40c: 8c 91 ld r24, X 40e: 83 8b std Z+19, r24 ; 0x13 in this function */ if (RB->tx_flag == 1){ spi->tx_len = RB->len; for (uint8_t i=0;i<(spi->tx_len+2);i++){ 410: 4f 5f subi r20, 0xFF ; 255 412: a4 2f mov r26, r20 414: b0 e0 ldi r27, 0x00 ; 0 416: 88 85 ldd r24, Y+8 ; 0x08 418: 90 e0 ldi r25, 0x00 ; 0 41a: 01 96 adiw r24, 0x01 ; 1 41c: 8a 17 cp r24, r26 41e: 9b 07 cpc r25, r27 420: 84 f7 brge .-32 ; 0x402 422: 20 c0 rjmp .+64 ; 0x464 spi->tx_buffer[i] = RB->buffer[i]; } RB->tx_flag = 0; spi->tx_flag = 1; }else if (echo->tx_flag == 1){ 424: 20 91 06 20 lds r18, 0x2006 428: 30 91 07 20 lds r19, 0x2007 42c: f9 01 movw r30, r18 42e: 83 85 ldd r24, Z+11 ; 0x0b 430: 81 30 cpi r24, 0x01 ; 1 432: e1 f4 brne .+56 ; 0x46c spi->tx_len = echo->len; 434: c0 91 02 20 lds r28, 0x2002 438: d0 91 03 20 lds r29, 0x2003 43c: 82 85 ldd r24, Z+10 ; 0x0a 43e: 88 87 std Y+8, r24 ; 0x08 440: 40 e0 ldi r20, 0x00 ; 0 442: 08 c0 rjmp .+16 ; 0x454 for (uint8_t i=0;i<(spi->tx_len+2);i++){ spi->tx_buffer[i] = echo->buffer[i]; 444: fe 01 movw r30, r28 446: ea 0f add r30, r26 448: fb 1f adc r31, r27 44a: a2 0f add r26, r18 44c: b3 1f adc r27, r19 44e: 8c 91 ld r24, X 450: 83 8b std Z+19, r24 ; 0x13 } RB->tx_flag = 0; spi->tx_flag = 1; }else if (echo->tx_flag == 1){ spi->tx_len = echo->len; for (uint8_t i=0;i<(spi->tx_len+2);i++){ 452: 4f 5f subi r20, 0xFF ; 255 454: a4 2f mov r26, r20 456: b0 e0 ldi r27, 0x00 ; 0 458: 88 85 ldd r24, Y+8 ; 0x08 45a: 90 e0 ldi r25, 0x00 ; 0 45c: 01 96 adiw r24, 0x01 ; 1 45e: 8a 17 cp r24, r26 460: 9b 07 cpc r25, r27 462: 84 f7 brge .-32 ; 0x444 spi->tx_buffer[i] = echo->buffer[i]; } echo->tx_flag = 0; 464: f9 01 movw r30, r18 466: 13 86 std Z+11, r1 ; 0x0b spi->tx_flag = 1; 468: 81 e0 ldi r24, 0x01 ; 1 46a: 8a 83 std Y+2, r24 ; 0x02 } } 46c: df 91 pop r29 46e: cf 91 pop r28 470: 08 95 ret 00000472 : void Process_Receive_Buffers(void){ 472: cf 93 push r28 474: df 93 push r29 /* This function processes received messages based on their content and such */ if ((spi->rx_flag) == 1){ 476: 20 91 02 20 lds r18, 0x2002 47a: 30 91 03 20 lds r19, 0x2003 47e: d9 01 movw r26, r18 480: 11 96 adiw r26, 0x01 ; 1 482: 8c 91 ld r24, X 484: 11 97 sbiw r26, 0x01 ; 1 486: 81 30 cpi r24, 0x01 ; 1 488: 69 f5 brne .+90 ; 0x4e4 if (spi->rx_buffer[0] == 0x01){ 48a: 19 96 adiw r26, 0x09 ; 9 48c: 8c 91 ld r24, X 48e: 81 30 cpi r24, 0x01 ; 1 490: 31 f0 breq .+12 ; 0x49e /* This function Echo's whatever is sent through spi */ void Echo(void){ if ((spi->rx_flag) == 1){ //if ((spi->rx_buffer[0] == 0x00) && (spi->rx_buffer[1] = 0x00)){ for(uint8_t i=0;i<(spi->rx_len+2);i++){ echo->buffer[i] = spi->rx_buffer[i]; 492: c0 91 06 20 lds r28, 0x2006 496: d0 91 07 20 lds r29, 0x2007 49a: 40 e0 ldi r20, 0x00 ; 0 49c: 16 c0 rjmp .+44 ; 0x4ca void Process_Receive_Buffers(void){ /* This function processes received messages based on their content and such */ if ((spi->rx_flag) == 1){ if (spi->rx_buffer[0] == 0x01){ fake_od->address = spi->rx_buffer[2]; 49e: e0 91 00 20 lds r30, 0x2000 4a2: f0 91 01 20 lds r31, 0x2001 4a6: d9 01 movw r26, r18 4a8: 1b 96 adiw r26, 0x0b ; 11 4aa: 8c 91 ld r24, X 4ac: 82 83 std Z+2, r24 ; 0x02 PORTE.OUTTGL = PIN5_bm; 4ae: 80 e2 ldi r24, 0x20 ; 32 4b0: e0 e8 ldi r30, 0x80 ; 128 4b2: f6 e0 ldi r31, 0x06 ; 6 4b4: 87 83 std Z+7, r24 ; 0x07 4b6: 16 c0 rjmp .+44 ; 0x4e4 /* This function Echo's whatever is sent through spi */ void Echo(void){ if ((spi->rx_flag) == 1){ //if ((spi->rx_buffer[0] == 0x00) && (spi->rx_buffer[1] = 0x00)){ for(uint8_t i=0;i<(spi->rx_len+2);i++){ echo->buffer[i] = spi->rx_buffer[i]; 4b8: fe 01 movw r30, r28 4ba: ea 0f add r30, r26 4bc: fb 1f adc r31, r27 4be: a2 0f add r26, r18 4c0: b3 1f adc r27, r19 4c2: 19 96 adiw r26, 0x09 ; 9 4c4: 8c 91 ld r24, X 4c6: 80 83 st Z, r24 /* This function Echo's whatever is sent through spi */ void Echo(void){ if ((spi->rx_flag) == 1){ //if ((spi->rx_buffer[0] == 0x00) && (spi->rx_buffer[1] = 0x00)){ for(uint8_t i=0;i<(spi->rx_len+2);i++){ 4c8: 4f 5f subi r20, 0xFF ; 255 4ca: f9 01 movw r30, r18 4cc: 57 81 ldd r21, Z+7 ; 0x07 4ce: a4 2f mov r26, r20 4d0: b0 e0 ldi r27, 0x00 ; 0 4d2: 85 2f mov r24, r21 4d4: 90 e0 ldi r25, 0x00 ; 0 4d6: 01 96 adiw r24, 0x01 ; 1 4d8: 8a 17 cp r24, r26 4da: 9b 07 cpc r25, r27 4dc: 6c f7 brge .-38 ; 0x4b8 echo->buffer[i] = spi->rx_buffer[i]; } echo->len = spi->rx_len; 4de: 5a 87 std Y+10, r21 ; 0x0a echo->tx_flag = 1; // Remember to ask to transmit buffer 4e0: 81 e0 ldi r24, 0x01 ; 1 4e2: 8b 87 std Y+11, r24 ; 0x0b PORTE.OUTTGL = PIN5_bm; }else{ Echo(); } } spi->rx_flag = 0; 4e4: d9 01 movw r26, r18 4e6: 11 96 adiw r26, 0x01 ; 1 4e8: 1c 92 st X, r1 } 4ea: df 91 pop r29 4ec: cf 91 pop r28 4ee: 08 95 ret 000004f0 : /* This function writes the heartbeat buffer when the heartbeat interrupt is fired */ void Make_RB(void){ //if (spi->first_message == 1){ if (RB->int_flag == 1){ 4f0: a0 91 04 20 lds r26, 0x2004 4f4: b0 91 05 20 lds r27, 0x2005 4f8: 1c 96 adiw r26, 0x0c ; 12 4fa: 8c 91 ld r24, X 4fc: 1c 97 sbiw r26, 0x0c ; 12 4fe: 81 30 cpi r24, 0x01 ; 1 500: 59 f5 brne .+86 ; 0x558 //PORTE.OUTTGL = PIN5_bm; RB->tx_flag = 1; 502: 1b 96 adiw r26, 0x0b ; 11 504: 8c 93 st X, r24 506: 1b 97 sbiw r26, 0x0b ; 11 RB->buffer[0] = (uint8_t)(RB_HEARTBEAT>>8); 508: 87 e0 ldi r24, 0x07 ; 7 50a: 8c 93 st X, r24 RB->buffer[1] = fake_od->address; 50c: e0 91 00 20 lds r30, 0x2000 510: f0 91 01 20 lds r31, 0x2001 514: 82 81 ldd r24, Z+2 ; 0x02 516: 11 96 adiw r26, 0x01 ; 1 518: 8c 93 st X, r24 51a: 11 97 sbiw r26, 0x01 ; 1 RB->buffer[2] = 0x67; 51c: 87 e6 ldi r24, 0x67 ; 103 51e: 12 96 adiw r26, 0x02 ; 2 520: 8c 93 st X, r24 522: 12 97 sbiw r26, 0x02 ; 2 RB->buffer[3] = 0x68; 524: 88 e6 ldi r24, 0x68 ; 104 526: 13 96 adiw r26, 0x03 ; 3 528: 8c 93 st X, r24 52a: 13 97 sbiw r26, 0x03 ; 3 RB->buffer[4] = 0x69; 52c: 89 e6 ldi r24, 0x69 ; 105 52e: 14 96 adiw r26, 0x04 ; 4 530: 8c 93 st X, r24 532: 14 97 sbiw r26, 0x04 ; 4 RB->buffer[5] = 0x70; 534: 80 e7 ldi r24, 0x70 ; 112 536: 15 96 adiw r26, 0x05 ; 5 538: 8c 93 st X, r24 53a: 15 97 sbiw r26, 0x05 ; 5 RB->buffer[6] = 0x71; 53c: 81 e7 ldi r24, 0x71 ; 113 53e: 16 96 adiw r26, 0x06 ; 6 540: 8c 93 st X, r24 542: 16 97 sbiw r26, 0x06 ; 6 RB->buffer[7] = 0x72; 544: 82 e7 ldi r24, 0x72 ; 114 546: 17 96 adiw r26, 0x07 ; 7 548: 8c 93 st X, r24 54a: 17 97 sbiw r26, 0x07 ; 7 RB->len = 6; 54c: 86 e0 ldi r24, 0x06 ; 6 54e: 1a 96 adiw r26, 0x0a ; 10 550: 8c 93 st X, r24 552: 1a 97 sbiw r26, 0x0a ; 10 RB->int_flag = 0; 554: 1c 96 adiw r26, 0x0c ; 12 556: 1c 92 st X, r1 558: 08 95 ret 0000055a : } //} } /* This function Echo's whatever is sent through spi */ void Echo(void){ 55a: cf 93 push r28 55c: df 93 push r29 if ((spi->rx_flag) == 1){ 55e: 20 91 02 20 lds r18, 0x2002 562: 30 91 03 20 lds r19, 0x2003 566: f9 01 movw r30, r18 568: 81 81 ldd r24, Z+1 ; 0x01 56a: 81 30 cpi r24, 0x01 ; 1 56c: e1 f4 brne .+56 ; 0x5a6 //if ((spi->rx_buffer[0] == 0x00) && (spi->rx_buffer[1] = 0x00)){ for(uint8_t i=0;i<(spi->rx_len+2);i++){ echo->buffer[i] = spi->rx_buffer[i]; 56e: c0 91 06 20 lds r28, 0x2006 572: d0 91 07 20 lds r29, 0x2007 576: 40 e0 ldi r20, 0x00 ; 0 578: 09 c0 rjmp .+18 ; 0x58c 57a: fe 01 movw r30, r28 57c: ea 0f add r30, r26 57e: fb 1f adc r31, r27 580: a2 0f add r26, r18 582: b3 1f adc r27, r19 584: 19 96 adiw r26, 0x09 ; 9 586: 8c 91 ld r24, X 588: 80 83 st Z, r24 /* This function Echo's whatever is sent through spi */ void Echo(void){ if ((spi->rx_flag) == 1){ //if ((spi->rx_buffer[0] == 0x00) && (spi->rx_buffer[1] = 0x00)){ for(uint8_t i=0;i<(spi->rx_len+2);i++){ 58a: 4f 5f subi r20, 0xFF ; 255 58c: f9 01 movw r30, r18 58e: 57 81 ldd r21, Z+7 ; 0x07 590: a4 2f mov r26, r20 592: b0 e0 ldi r27, 0x00 ; 0 594: 85 2f mov r24, r21 596: 90 e0 ldi r25, 0x00 ; 0 598: 01 96 adiw r24, 0x01 ; 1 59a: 8a 17 cp r24, r26 59c: 9b 07 cpc r25, r27 59e: 6c f7 brge .-38 ; 0x57a echo->buffer[i] = spi->rx_buffer[i]; } echo->len = spi->rx_len; 5a0: 5a 87 std Y+10, r21 ; 0x0a echo->tx_flag = 1; // Remember to ask to transmit buffer 5a2: 81 e0 ldi r24, 0x01 ; 1 5a4: 8b 87 std Y+11, r24 ; 0x0b //} } } 5a6: df 91 pop r29 5a8: cf 91 pop r28 5aa: 08 95 ret 000005ac <__vector_24>: /* This is an interrupt should have as little processing as possible in order to reduce interference */ ISR(SPIC_INT_vect){ 5ac: 1f 92 push r1 5ae: 0f 92 push r0 5b0: 0f b6 in r0, 0x3f ; 63 5b2: 0f 92 push r0 5b4: 08 b6 in r0, 0x38 ; 56 5b6: 0f 92 push r0 5b8: 0b b6 in r0, 0x3b ; 59 5ba: 0f 92 push r0 5bc: 11 24 eor r1, r1 5be: 18 be out 0x38, r1 ; 56 5c0: 1b be out 0x3b, r1 ; 59 5c2: 8f 93 push r24 5c4: ef 93 push r30 5c6: ff 93 push r31 /* Set the interrupt flag to true so that the main loop will process the message. */ spi->int_flag = 1; 5c8: e0 91 02 20 lds r30, 0x2002 5cc: f0 91 03 20 lds r31, 0x2003 5d0: 81 e0 ldi r24, 0x01 ; 1 5d2: 80 83 st Z, r24 return; } 5d4: ff 91 pop r31 5d6: ef 91 pop r30 5d8: 8f 91 pop r24 5da: 0f 90 pop r0 5dc: 0b be out 0x3b, r0 ; 59 5de: 0f 90 pop r0 5e0: 08 be out 0x38, r0 ; 56 5e2: 0f 90 pop r0 5e4: 0f be out 0x3f, r0 ; 63 5e6: 0f 90 pop r0 5e8: 1f 90 pop r1 5ea: 18 95 reti 000005ec <__vector_14>: /* Heartbeat interrupt */ ISR(TCC0_OVF_vect){ 5ec: 1f 92 push r1 5ee: 0f 92 push r0 5f0: 0f b6 in r0, 0x3f ; 63 5f2: 0f 92 push r0 5f4: 08 b6 in r0, 0x38 ; 56 5f6: 0f 92 push r0 5f8: 0b b6 in r0, 0x3b ; 59 5fa: 0f 92 push r0 5fc: 11 24 eor r1, r1 5fe: 18 be out 0x38, r1 ; 56 600: 1b be out 0x3b, r1 ; 59 602: 8f 93 push r24 604: ef 93 push r30 606: ff 93 push r31 /* Set the heartbeat timer flag so that the main loop will proces the message */ RB->int_flag = 1; 608: e0 91 04 20 lds r30, 0x2004 60c: f0 91 05 20 lds r31, 0x2005 610: 81 e0 ldi r24, 0x01 ; 1 612: 84 87 std Z+12, r24 ; 0x0c return; } 614: ff 91 pop r31 616: ef 91 pop r30 618: 8f 91 pop r24 61a: 0f 90 pop r0 61c: 0b be out 0x3b, r0 ; 59 61e: 0f 90 pop r0 620: 08 be out 0x38, r0 ; 56 622: 0f 90 pop r0 624: 0f be out 0x3f, r0 ; 63 626: 0f 90 pop r0 628: 1f 90 pop r1 62a: 18 95 reti 0000062c : CLKSYS_Main_ClockSource_Select(CLK_SCLKSEL_RC32M_gc); return; } /* --------------------------------------------------------------- */ void PWMTimer(void){ 62c: 0f 93 push r16 62e: 1f 93 push r17 uint16_t compareValue = 0x0069; PORTF.DIR = 0xFF; // note: bitmask this foo! 630: 8f ef ldi r24, 0xFF ; 255 632: 80 93 a0 06 sts 0x06A0, r24 TC_SetPeriod (&TCF0, 0x00D2); //Set TC period 636: 00 e0 ldi r16, 0x00 ; 0 638: 1b e0 ldi r17, 0x0B ; 11 63a: 82 ed ldi r24, 0xD2 ; 210 63c: 90 e0 ldi r25, 0x00 ; 0 63e: f8 01 movw r30, r16 640: 86 a3 std Z+38, r24 ; 0x26 642: 97 a3 std Z+39, r25 ; 0x27 TC0_ConfigWGM (&TCF0, TC_WGMODE_SS_gc); //Single slope mode 644: 80 e0 ldi r24, 0x00 ; 0 646: 9b e0 ldi r25, 0x0B ; 11 648: 63 e0 ldi r22, 0x03 ; 3 64a: 0e 94 ae 05 call 0xb5c ; 0xb5c TC0_EnableCCChannels( &TCF0, TC0_CCAEN_bm); //Enable compare channel A 64e: 80 e0 ldi r24, 0x00 ; 0 650: 9b e0 ldi r25, 0x0B ; 11 652: 60 e1 ldi r22, 0x10 ; 16 654: 0e 94 c8 05 call 0xb90 ; 0xb90 TC0_ConfigClockSource( &TCF0, TC_CLKSEL_DIV1_gc); //Start timer by selecting clock source 658: 80 e0 ldi r24, 0x00 ; 0 65a: 9b e0 ldi r25, 0x0B ; 11 65c: 61 e0 ldi r22, 0x01 ; 1 65e: 0e 94 a2 05 call 0xb44 ; 0xb44 TC_SetCompareA (&TCF0, compareValue); //Setting our compare value 662: 89 e6 ldi r24, 0x69 ; 105 664: 90 e0 ldi r25, 0x00 ; 0 666: f8 01 movw r30, r16 668: 80 af std Z+56, r24 ; 0x38 66a: 91 af std Z+57, r25 ; 0x39 return; } 66c: 1f 91 pop r17 66e: 0f 91 pop r16 670: 08 95 ret 00000672 : /* --------------------------------------------------------------- */ void CLK32Change(void){ /*Enable the internal 32MHz ring oscillator, wait till its stable and set as the main system clock*/ CLKSYS_Enable(OSC_RC32MEN_bm); 672: 80 91 50 00 lds r24, 0x0050 676: 82 60 ori r24, 0x02 ; 2 678: 80 93 50 00 sts 0x0050, r24 67c: 03 c0 rjmp .+6 ; 0x684 while (CLKSYS_IsReady(OSC_RC32MRDY_bm) == 0) CLKSYS_Main_ClockSource_Select(CLK_SCLKSEL_RC32M_gc); 67e: 81 e0 ldi r24, 0x01 ; 1 680: 0e 94 2e 05 call 0xa5c ; 0xa5c void CLK32Change(void){ /*Enable the internal 32MHz ring oscillator, wait till its stable and set as the main system clock*/ CLKSYS_Enable(OSC_RC32MEN_bm); while (CLKSYS_IsReady(OSC_RC32MRDY_bm) == 0) 684: 80 91 51 00 lds r24, 0x0051 688: 81 ff sbrs r24, 1 68a: f9 cf rjmp .-14 ; 0x67e CLKSYS_Main_ClockSource_Select(CLK_SCLKSEL_RC32M_gc); return; } 68c: 08 95 ret 0000068e : Make_RB(); } } void SPIinit(void){ 68e: ef 92 push r14 690: 0f 93 push r16 //initialize SPI slave on port C SPI_SlaveInit (&spiSlaveC, //note: these might change for pic interface 692: 88 e0 ldi r24, 0x08 ; 8 694: 90 e2 ldi r25, 0x20 ; 32 696: 60 ec ldi r22, 0xC0 ; 192 698: 78 e0 ldi r23, 0x08 ; 8 69a: 40 e4 ldi r20, 0x40 ; 64 69c: 56 e0 ldi r21, 0x06 ; 6 69e: 20 e0 ldi r18, 0x00 ; 0 6a0: 04 e0 ldi r16, 0x04 ; 4 6a2: 32 e0 ldi r19, 0x02 ; 2 6a4: e3 2e mov r14, r19 6a6: 0e 94 e4 03 call 0x7c8 ; 0x7c8 false, SPI_MODE_1_gc, SPI_INTLVL_MED_gc); //Enable low and medium interrupts in teh interrupt controller PMIC.CTRL |= PMIC_MEDLVLEN_bm | PMIC_LOLVLEN_bm; 6aa: e0 ea ldi r30, 0xA0 ; 160 6ac: f0 e0 ldi r31, 0x00 ; 0 6ae: 82 81 ldd r24, Z+2 ; 0x02 6b0: 83 60 ori r24, 0x03 ; 3 6b2: 82 83 std Z+2, r24 ; 0x02 sei(); 6b4: 78 94 sei return; } 6b6: 0f 91 pop r16 6b8: ef 90 pop r14 6ba: 08 95 ret 000006bc
: void Echo(void); void Make_RB(void); int main(void){ fake_od->address = RB_NODEID; 6bc: e0 91 00 20 lds r30, 0x2000 6c0: f0 91 01 20 lds r31, 0x2001 6c4: 12 82 std Z+2, r1 ; 0x02 /* Set SS_PIC pin to output */ PORTD.DIR = 0b00000001; 6c6: 91 e0 ldi r25, 0x01 ; 1 6c8: 90 93 60 06 sts 0x0660, r25 /* Set Pins 1,4,5 for LED outputs */ PORTE.DIR = 0b00110010; 6cc: 82 e3 ldi r24, 0x32 ; 50 6ce: 80 93 80 06 sts 0x0680, r24 PORTD.OUT = PIN0_bm; 6d2: e0 e6 ldi r30, 0x60 ; 96 6d4: f6 e0 ldi r31, 0x06 ; 6 6d6: 94 83 std Z+4, r25 ; 0x04 i = 0; 6d8: 10 92 45 20 sts 0x2045, r1 6dc: 10 92 46 20 sts 0x2046, r1 spi->int_flag = 0; 6e0: e0 91 02 20 lds r30, 0x2002 6e4: f0 91 03 20 lds r31, 0x2003 6e8: 10 82 st Z, r1 SPIinit(); 6ea: 0e 94 47 03 call 0x68e ; 0x68e CLK32Change(); 6ee: 0e 94 39 03 call 0x672 ; 0x672 6f2: 80 e1 ldi r24, 0x10 ; 16 6f4: 97 e2 ldi r25, 0x27 ; 39 milliseconds can be achieved. */ void _delay_loop_2(uint16_t __count) { __asm__ volatile ( 6f6: 20 e2 ldi r18, 0x20 ; 32 6f8: 33 e0 ldi r19, 0x03 ; 3 6fa: f9 01 movw r30, r18 6fc: 31 97 sbiw r30, 0x01 ; 1 6fe: f1 f7 brne .-4 ; 0x6fc __ticks = (uint16_t) (__ms * 10.0); while(__ticks) { // wait 1/10 ms _delay_loop_2(((F_CPU) / 4e3) / 10); __ticks --; 700: 01 97 sbiw r24, 0x01 ; 1 __ticks = 1; else if (__tmp > 65535) { // __ticks = requested delay in 1/10 ms __ticks = (uint16_t) (__ms * 10.0); while(__ticks) 702: d9 f7 brne .-10 ; 0x6fa /* Wait for new clock to stabalize */ _delay_ms(1000); PWMTimer(); 704: 0e 94 16 03 call 0x62c ; 0x62c Set up Timer/Counter 0 to work from CPICLK/64 with period of 31500 (a frequency of about 1 Hz) and enable overflow interrupt note: Initializing this timere will instantiate a heartbeat by nature of the interrupt linked to it */ TCC0.PER = 31650; 708: e0 e0 ldi r30, 0x00 ; 0 70a: f8 e0 ldi r31, 0x08 ; 8 70c: 82 ea ldi r24, 0xA2 ; 162 70e: 9b e7 ldi r25, 0x7B ; 123 710: 86 a3 std Z+38, r24 ; 0x26 712: 97 a3 std Z+39, r25 ; 0x27 TCC0.CTRLA = (TCC0.CTRLA & ~TC0_CLKSEL_gm) | TC_CLKSEL_DIV1024_gc; 714: 80 91 00 08 lds r24, 0x0800 718: 80 7f andi r24, 0xF0 ; 240 71a: 87 60 ori r24, 0x07 ; 7 71c: 80 93 00 08 sts 0x0800, r24 TCC0.INTCTRLA = (TCC0.INTCTRLA & ~TC0_OVFINTLVL_gm) | 720: 80 91 06 08 lds r24, 0x0806 724: 8c 7f andi r24, 0xFC ; 252 726: 82 60 ori r24, 0x02 ; 2 728: 86 83 std Z+6, r24 ; 0x06 TC_OVFINTLVL_MED_gc; PMIC.CTRL |= PMIC_MEDLVLEN_bm; 72a: 80 91 a2 00 lds r24, 0x00A2 72e: 82 60 ori r24, 0x02 ; 2 730: e0 ea ldi r30, 0xA0 ; 160 732: f0 e0 ldi r31, 0x00 ; 0 734: 82 83 std Z+2, r24 ; 0x02 736: e0 91 02 20 lds r30, 0x2002 73a: f0 91 03 20 lds r31, 0x2003 73e: 82 e0 ldi r24, 0x02 ; 2 spi->tx_buffer[6] = 0x04; spi->tx_buffer[7] = 0x05; spi->tx_buffer[8] = 0x06; spi->tx_buffer[9] = 0x35;*/ for(uint8_t i=2;itx_buffer[i] = 0x00; 740: 15 8a std Z+21, r1 ; 0x15 spi->tx_buffer[5] = 0x03; spi->tx_buffer[6] = 0x04; spi->tx_buffer[7] = 0x05; spi->tx_buffer[8] = 0x06; spi->tx_buffer[9] = 0x35;*/ for(uint8_t i=2;i spi->tx_buffer[i] = 0x00; } PORTE.OUT = PIN1_bm; 74a: 82 e0 ldi r24, 0x02 ; 2 74c: e0 e8 ldi r30, 0x80 ; 128 74e: f6 e0 ldi r31, 0x06 ; 6 750: 84 83 std Z+4, r24 ; 0x04 for(;;){ Process_SPI(); 752: 0e 94 36 01 call 0x26c ; 0x26c Process_Transmit_Buffers(); 756: 0e 94 ef 01 call 0x3de ; 0x3de Process_Receive_Buffers(); 75a: 0e 94 39 02 call 0x472 ; 0x472 Make_RB(); 75e: 0e 94 78 02 call 0x4f0 ; 0x4f0 762: f7 cf rjmp .-18 ; 0x752 00000764 : bool lsbFirst, SPI_MODE_t mode, SPI_INTLVL_t intLevel, bool clk2x, SPI_PRESCALER_t clockDivision) { 764: af 92 push r10 766: cf 92 push r12 768: ef 92 push r14 76a: 0f 93 push r16 76c: dc 01 movw r26, r24 76e: fb 01 movw r30, r22 spi->module = module; 770: 6d 93 st X+, r22 772: 7c 93 st X, r23 774: 11 97 sbiw r26, 0x01 ; 1 spi->port = port; 776: 12 96 adiw r26, 0x02 ; 2 778: 4d 93 st X+, r20 77a: 5c 93 st X, r21 77c: 13 97 sbiw r26, 0x03 ; 3 spi->interrupted = false; 77e: 14 96 adiw r26, 0x04 ; 4 780: 1c 92 st X, r1 782: 14 97 sbiw r26, 0x04 ; 4 spi->module->CTRL = clockDivision | /* SPI prescaler. */ 784: cc 20 and r12, r12 786: 11 f4 brne .+4 ; 0x78c 788: 90 e0 ldi r25, 0x00 ; 0 78a: 01 c0 rjmp .+2 ; 0x78e 78c: 90 e8 ldi r25, 0x80 ; 128 78e: 22 23 and r18, r18 790: 11 f4 brne .+4 ; 0x796 792: 80 e0 ldi r24, 0x00 ; 0 794: 01 c0 rjmp .+2 ; 0x798 796: 80 e2 ldi r24, 0x20 ; 32 798: 00 65 ori r16, 0x50 ; 80 79a: 0a 29 or r16, r10 79c: 90 2b or r25, r16 79e: 89 2b or r24, r25 7a0: 80 83 st Z, r24 (lsbFirst ? SPI_DORD_bm : 0) | /* Data order. */ SPI_MASTER_bm | /* SPI master. */ mode; /* SPI mode. */ /* Interrupt level. */ spi->module->INTCTRL = intLevel; 7a2: ed 91 ld r30, X+ 7a4: fc 91 ld r31, X 7a6: 11 97 sbiw r26, 0x01 ; 1 7a8: e1 82 std Z+1, r14 ; 0x01 /* No assigned data packet. */ spi->dataPacket = NULL; 7aa: 15 96 adiw r26, 0x05 ; 5 7ac: 1d 92 st X+, r1 7ae: 1c 92 st X, r1 7b0: 16 97 sbiw r26, 0x06 ; 6 /* MOSI and SCK as output. */ spi->port->DIRSET = SPI_MOSI_bm | SPI_SCK_bm; 7b2: 12 96 adiw r26, 0x02 ; 2 7b4: ed 91 ld r30, X+ 7b6: fc 91 ld r31, X 7b8: 13 97 sbiw r26, 0x03 ; 3 7ba: 80 ea ldi r24, 0xA0 ; 160 7bc: 81 83 std Z+1, r24 ; 0x01 } 7be: 0f 91 pop r16 7c0: ef 90 pop r14 7c2: cf 90 pop r12 7c4: af 90 pop r10 7c6: 08 95 ret 000007c8 : SPI_t *module, PORT_t *port, bool lsbFirst, SPI_MODE_t mode, SPI_INTLVL_t intLevel) { 7c8: ef 92 push r14 7ca: 0f 93 push r16 7cc: dc 01 movw r26, r24 7ce: fb 01 movw r30, r22 /* SPI module. */ spi->module = module; 7d0: 6d 93 st X+, r22 7d2: 7c 93 st X, r23 7d4: 11 97 sbiw r26, 0x01 ; 1 spi->port = port; 7d6: 12 96 adiw r26, 0x02 ; 2 7d8: 4d 93 st X+, r20 7da: 5c 93 st X, r21 7dc: 13 97 sbiw r26, 0x03 ; 3 spi->module->CTRL = SPI_ENABLE_bm | /* Enable SPI module. */ 7de: 22 23 and r18, r18 7e0: 11 f4 brne .+4 ; 0x7e6 7e2: 80 e4 ldi r24, 0x40 ; 64 7e4: 01 c0 rjmp .+2 ; 0x7e8 7e6: 80 e6 ldi r24, 0x60 ; 96 7e8: 80 2b or r24, r16 7ea: 80 83 st Z, r24 (lsbFirst ? SPI_DORD_bm : 0) | /* Data order. */ mode; /* SPI mode. */ /* Interrupt level. */ spi->module->INTCTRL = intLevel; 7ec: ed 91 ld r30, X+ 7ee: fc 91 ld r31, X 7f0: 11 97 sbiw r26, 0x01 ; 1 7f2: e1 82 std Z+1, r14 ; 0x01 /* MISO as output. */ spi->port->DIRSET = SPI_MISO_bm; 7f4: 12 96 adiw r26, 0x02 ; 2 7f6: ed 91 ld r30, X+ 7f8: fc 91 ld r31, X 7fa: 13 97 sbiw r26, 0x03 ; 3 7fc: 80 e4 ldi r24, 0x40 ; 64 7fe: 81 83 std Z+1, r24 ; 0x01 } 800: 0f 91 pop r16 802: ef 90 pop r14 804: 08 95 ret 00000806 : const uint8_t *transmitData, uint8_t *receiveData, uint8_t bytesToTransceive, PORT_t *ssPort, uint8_t ssPinMask) { 806: ef 92 push r14 808: 0f 93 push r16 80a: 1f 93 push r17 80c: fc 01 movw r30, r24 dataPacket->ssPort = ssPort; 80e: 00 83 st Z, r16 810: 11 83 std Z+1, r17 ; 0x01 dataPacket->ssPinMask = ssPinMask; 812: e2 82 std Z+2, r14 ; 0x02 dataPacket->transmitData = transmitData; 814: 63 83 std Z+3, r22 ; 0x03 816: 74 83 std Z+4, r23 ; 0x04 dataPacket->receiveData = receiveData; 818: 45 83 std Z+5, r20 ; 0x05 81a: 56 83 std Z+6, r21 ; 0x06 dataPacket->bytesToTransceive = bytesToTransceive; 81c: 27 83 std Z+7, r18 ; 0x07 dataPacket->bytesTransceived = 0; 81e: 10 86 std Z+8, r1 ; 0x08 dataPacket->complete = false; 820: 11 86 std Z+9, r1 ; 0x09 } 822: 1f 91 pop r17 824: 0f 91 pop r16 826: ef 90 pop r14 828: 08 95 ret 0000082a : * a pointer to the related SPI_Master_t struct as argument. * * \param spi Pointer to the modules own SPI_Master_t struct. */ void SPI_MasterInterruptHandler(SPI_Master_t *spi) { 82a: cf 93 push r28 82c: df 93 push r29 82e: dc 01 movw r26, r24 uint8_t data; uint8_t bytesTransceived = spi->dataPacket->bytesTransceived; 830: 15 96 adiw r26, 0x05 ; 5 832: cd 91 ld r28, X+ 834: dc 91 ld r29, X 836: 16 97 sbiw r26, 0x06 ; 6 838: 98 85 ldd r25, Y+8 ; 0x08 /* If SS pin interrupt (SS used and pulled low). * No data received at this point. */ if ( !(spi->module->CTRL & SPI_MASTER_bm) ) { 83a: ed 91 ld r30, X+ 83c: fc 91 ld r31, X 83e: 11 97 sbiw r26, 0x01 ; 1 840: 80 81 ld r24, Z 842: 84 fd sbrc r24, 4 844: 05 c0 rjmp .+10 ; 0x850 spi->interrupted = true; 846: 81 e0 ldi r24, 0x01 ; 1 848: 14 96 adiw r26, 0x04 ; 4 84a: 8c 93 st X, r24 84c: 14 97 sbiw r26, 0x04 ; 4 84e: 24 c0 rjmp .+72 ; 0x898 } else { /* Data interrupt. */ /* Store received data. */ data = spi->module->DATA; 850: 83 81 ldd r24, Z+3 ; 0x03 spi->dataPacket->receiveData[bytesTransceived] = data; 852: ed 81 ldd r30, Y+5 ; 0x05 854: fe 81 ldd r31, Y+6 ; 0x06 856: e9 0f add r30, r25 858: f1 1d adc r31, r1 85a: 80 83 st Z, r24 /* Next byte. */ bytesTransceived++; 85c: 9f 5f subi r25, 0xFF ; 255 /* If more data. */ if (bytesTransceived < spi->dataPacket->bytesToTransceive) { 85e: 15 96 adiw r26, 0x05 ; 5 860: ed 91 ld r30, X+ 862: fc 91 ld r31, X 864: 16 97 sbiw r26, 0x06 ; 6 866: 87 81 ldd r24, Z+7 ; 0x07 868: 98 17 cp r25, r24 86a: 58 f4 brcc .+22 ; 0x882 /* Put data byte in transmit data register. */ data = spi->dataPacket->transmitData[bytesTransceived]; 86c: 03 80 ldd r0, Z+3 ; 0x03 86e: f4 81 ldd r31, Z+4 ; 0x04 870: e0 2d mov r30, r0 872: e9 0f add r30, r25 874: f1 1d adc r31, r1 876: 80 81 ld r24, Z spi->module->DATA = data; 878: ed 91 ld r30, X+ 87a: fc 91 ld r31, X 87c: 11 97 sbiw r26, 0x01 ; 1 87e: 83 83 std Z+3, r24 ; 0x03 880: 0b c0 rjmp .+22 ; 0x898 /* Transmission complete. */ else { /* Release SS to slave(s). */ uint8_t ssPinMask = spi->dataPacket->ssPinMask; 882: 82 81 ldd r24, Z+2 ; 0x02 SPI_MasterSSHigh(spi->dataPacket->ssPort, ssPinMask); 884: 01 90 ld r0, Z+ 886: f0 81 ld r31, Z 888: e0 2d mov r30, r0 88a: 85 83 std Z+5, r24 ; 0x05 spi->dataPacket->complete = true; 88c: 15 96 adiw r26, 0x05 ; 5 88e: ed 91 ld r30, X+ 890: fc 91 ld r31, X 892: 16 97 sbiw r26, 0x06 ; 6 894: 81 e0 ldi r24, 0x01 ; 1 896: 81 87 std Z+9, r24 ; 0x09 } } /* Write back bytesTransceived to data packet. */ spi->dataPacket->bytesTransceived = bytesTransceived; 898: 15 96 adiw r26, 0x05 ; 5 89a: ed 91 ld r30, X+ 89c: fc 91 ld r31, X 89e: 16 97 sbiw r26, 0x06 ; 6 8a0: 90 87 std Z+8, r25 ; 0x08 } 8a2: df 91 pop r29 8a4: cf 91 pop r28 8a6: 08 95 ret 000008a8 : * \retval SPI_BUSY The SPI module is busy. * \retval SPI_INTERRUPTED The transmission was interrupted by another master. */ uint8_t SPI_MasterInterruptTransceivePacket(SPI_Master_t *spi, SPI_DataPacket_t *dataPacket) { 8a8: cf 93 push r28 8aa: df 93 push r29 8ac: dc 01 movw r26, r24 8ae: eb 01 movw r28, r22 uint8_t data; bool interrupted = spi->interrupted; 8b0: 14 96 adiw r26, 0x04 ; 4 8b2: 9c 91 ld r25, X 8b4: 14 97 sbiw r26, 0x04 ; 4 /* If no packets sent so far. */ if (spi->dataPacket == NULL) { 8b6: 15 96 adiw r26, 0x05 ; 5 8b8: ed 91 ld r30, X+ 8ba: fc 91 ld r31, X 8bc: 16 97 sbiw r26, 0x06 ; 6 8be: 30 97 sbiw r30, 0x00 ; 0 8c0: 29 f4 brne .+10 ; 0x8cc spi->dataPacket = dataPacket; 8c2: 15 96 adiw r26, 0x05 ; 5 8c4: 6d 93 st X+, r22 8c6: 7c 93 st X, r23 8c8: 16 97 sbiw r26, 0x06 ; 6 8ca: 10 c0 rjmp .+32 ; 0x8ec } /* If ongoing transmission. */ else if (spi->dataPacket->complete == false) { 8cc: 81 85 ldd r24, Z+9 ; 0x09 8ce: 88 23 and r24, r24 8d0: 11 f4 brne .+4 ; 0x8d6 8d2: 82 e0 ldi r24, 0x02 ; 2 8d4: 28 c0 rjmp .+80 ; 0x926 return (SPI_BUSY); } /* If interrupted by other master. */ else if (interrupted) { 8d6: 99 23 and r25, r25 8d8: 49 f0 breq .+18 ; 0x8ec /* If SS released. */ if (spi->port->OUT & SPI_SS_bm) { 8da: 12 96 adiw r26, 0x02 ; 2 8dc: ed 91 ld r30, X+ 8de: fc 91 ld r31, X 8e0: 13 97 sbiw r26, 0x03 ; 3 8e2: 84 81 ldd r24, Z+4 ; 0x04 8e4: 84 fd sbrc r24, 4 8e6: 02 c0 rjmp .+4 ; 0x8ec 8e8: 81 e0 ldi r24, 0x01 ; 1 8ea: 1d c0 rjmp .+58 ; 0x926 } } /* NOT interrupted by other master. * Start transmission. */ spi->dataPacket = dataPacket; 8ec: 15 96 adiw r26, 0x05 ; 5 8ee: cd 93 st X+, r28 8f0: dc 93 st X, r29 8f2: 16 97 sbiw r26, 0x06 ; 6 spi->dataPacket->complete = false; 8f4: 19 86 std Y+9, r1 ; 0x09 spi->interrupted = false; 8f6: 14 96 adiw r26, 0x04 ; 4 8f8: 1c 92 st X, r1 8fa: 14 97 sbiw r26, 0x04 ; 4 /* SS to slave(s) low.*/ uint8_t ssPinMask = spi->dataPacket->ssPinMask; 8fc: 8a 81 ldd r24, Y+2 ; 0x02 SPI_MasterSSLow(spi->dataPacket->ssPort, ssPinMask); 8fe: e8 81 ld r30, Y 900: f9 81 ldd r31, Y+1 ; 0x01 902: 86 83 std Z+6, r24 ; 0x06 spi->dataPacket->bytesTransceived = 0; 904: 15 96 adiw r26, 0x05 ; 5 906: ed 91 ld r30, X+ 908: fc 91 ld r31, X 90a: 16 97 sbiw r26, 0x06 ; 6 90c: 10 86 std Z+8, r1 ; 0x08 /* Start sending data. */ data = spi->dataPacket->transmitData[0]; 90e: 15 96 adiw r26, 0x05 ; 5 910: ed 91 ld r30, X+ 912: fc 91 ld r31, X 914: 16 97 sbiw r26, 0x06 ; 6 916: 03 80 ldd r0, Z+3 ; 0x03 918: f4 81 ldd r31, Z+4 ; 0x04 91a: e0 2d mov r30, r0 91c: 80 81 ld r24, Z spi->module->DATA = data; 91e: ed 91 ld r30, X+ 920: fc 91 ld r31, X 922: 83 83 std Z+3, r24 ; 0x03 924: 80 e0 ldi r24, 0x00 ; 0 /* Successs */ return (SPI_OK); } 926: df 91 pop r29 928: cf 91 pop r28 92a: 08 95 ret 0000092c : * \param TXdata Data to transmit to slave. * * \return Data received from slave. */ uint8_t SPI_MasterTransceiveByte(SPI_Master_t *spi, uint8_t TXdata) { 92c: fc 01 movw r30, r24 /* Send pattern. */ spi->module->DATA = TXdata; 92e: a0 81 ld r26, Z 930: b1 81 ldd r27, Z+1 ; 0x01 932: 13 96 adiw r26, 0x03 ; 3 934: 6c 93 st X, r22 /* Wait for transmission complete. */ while(!(spi->module->STATUS & SPI_IF_bm)) { 936: 01 90 ld r0, Z+ 938: f0 81 ld r31, Z 93a: e0 2d mov r30, r0 93c: 82 81 ldd r24, Z+2 ; 0x02 93e: 87 ff sbrs r24, 7 940: fd cf rjmp .-6 ; 0x93c } /* Read received data. */ uint8_t result = spi->module->DATA; 942: 83 81 ldd r24, Z+3 ; 0x03 return(result); } 944: 08 95 ret 00000946 : * \retval true Success * \retval false Failure */ bool SPI_MasterTransceivePacket(SPI_Master_t *spi, SPI_DataPacket_t *dataPacket) { 946: cf 93 push r28 948: df 93 push r29 94a: ec 01 movw r28, r24 94c: fb 01 movw r30, r22 /* Check if data packet has been created. */ if(dataPacket == NULL) { 94e: 61 15 cp r22, r1 950: 71 05 cpc r23, r1 952: 11 f4 brne .+4 ; 0x958 954: 80 e0 ldi r24, 0x00 ; 0 956: 37 c0 rjmp .+110 ; 0x9c6 return false; } /* Assign datapacket to SPI module. */ spi->dataPacket = dataPacket; 958: 6d 83 std Y+5, r22 ; 0x05 95a: 7e 83 std Y+6, r23 ; 0x06 uint8_t ssPinMask = spi->dataPacket->ssPinMask; 95c: 42 81 ldd r20, Z+2 ; 0x02 /* If SS signal to slave(s). */ if (spi->dataPacket->ssPort != NULL) { 95e: a0 81 ld r26, Z 960: b1 81 ldd r27, Z+1 ; 0x01 962: 10 97 sbiw r26, 0x00 ; 0 964: 11 f0 breq .+4 ; 0x96a /* SS to slave(s) low. */ SPI_MasterSSLow(spi->dataPacket->ssPort, ssPinMask); 966: 16 96 adiw r26, 0x06 ; 6 968: 4c 93 st X, r20 } /* Transceive bytes. */ uint8_t bytesTransceived = 0; uint8_t bytesToTransceive = dataPacket->bytesToTransceive; 96a: 67 81 ldd r22, Z+7 ; 0x07 96c: 90 e0 ldi r25, 0x00 ; 0 96e: 1a c0 rjmp .+52 ; 0x9a4 while (bytesTransceived < bytesToTransceive) { /* Send pattern. */ uint8_t data = spi->dataPacket->transmitData[bytesTransceived]; 970: 29 2f mov r18, r25 972: 30 e0 ldi r19, 0x00 ; 0 974: 03 80 ldd r0, Z+3 ; 0x03 976: f4 81 ldd r31, Z+4 ; 0x04 978: e0 2d mov r30, r0 97a: e2 0f add r30, r18 97c: f3 1f adc r31, r19 97e: 80 81 ld r24, Z spi->module->DATA = data; 980: e8 81 ld r30, Y 982: f9 81 ldd r31, Y+1 ; 0x01 984: 83 83 std Z+3, r24 ; 0x03 /* Wait for transmission complete. */ while(!(spi->module->STATUS & SPI_IF_bm)) { 986: e8 81 ld r30, Y 988: f9 81 ldd r31, Y+1 ; 0x01 98a: 82 81 ldd r24, Z+2 ; 0x02 98c: 87 ff sbrs r24, 7 98e: fd cf rjmp .-6 ; 0x98a } /* Read received data. */ data = spi->module->DATA; 990: 83 81 ldd r24, Z+3 ; 0x03 spi->dataPacket->receiveData[bytesTransceived] = data; 992: ed 81 ldd r30, Y+5 ; 0x05 994: fe 81 ldd r31, Y+6 ; 0x06 996: 05 80 ldd r0, Z+5 ; 0x05 998: f6 81 ldd r31, Z+6 ; 0x06 99a: e0 2d mov r30, r0 99c: e2 0f add r30, r18 99e: f3 1f adc r31, r19 9a0: 80 83 st Z, r24 bytesTransceived++; 9a2: 9f 5f subi r25, 0xFF ; 255 9a4: ed 81 ldd r30, Y+5 ; 0x05 9a6: fe 81 ldd r31, Y+6 ; 0x06 } /* Transceive bytes. */ uint8_t bytesTransceived = 0; uint8_t bytesToTransceive = dataPacket->bytesToTransceive; while (bytesTransceived < bytesToTransceive) { 9a8: 96 17 cp r25, r22 9aa: 10 f3 brcs .-60 ; 0x970 bytesTransceived++; } /* If SS signal to slave(s). */ if (spi->dataPacket->ssPort != NULL) { 9ac: 01 90 ld r0, Z+ 9ae: f0 81 ld r31, Z 9b0: e0 2d mov r30, r0 9b2: 30 97 sbiw r30, 0x00 ; 0 9b4: 09 f0 breq .+2 ; 0x9b8 /* Release SS to slave(s). */ SPI_MasterSSHigh(spi->dataPacket->ssPort, ssPinMask); 9b6: 45 83 std Z+5, r20 ; 0x05 } /* Set variables to indicate that transmission is complete. */ spi->dataPacket->bytesTransceived = bytesTransceived; 9b8: ed 81 ldd r30, Y+5 ; 0x05 9ba: fe 81 ldd r31, Y+6 ; 0x06 9bc: 60 87 std Z+8, r22 ; 0x08 spi->dataPacket->complete = true; 9be: ed 81 ldd r30, Y+5 ; 0x05 9c0: fe 81 ldd r31, Y+6 ; 0x06 9c2: 81 e0 ldi r24, 0x01 ; 1 9c4: 81 87 std Z+9, r24 ; 0x09 /* Report success. */ return true; } 9c6: df 91 pop r29 9c8: cf 91 pop r28 9ca: 08 95 ret 000009cc : * * \param address A pointer to the address to write to. * \param value The value to put in to the register. */ void CCPWrite( volatile uint8_t * address, uint8_t value ) { 9cc: 0f 93 push r16 9ce: df 93 push r29 9d0: cf 93 push r28 9d2: 0f 92 push r0 9d4: cd b7 in r28, 0x3d ; 61 9d6: de b7 in r29, 0x3e ; 62 // Restore global interrupt setting from scratch register. asm("out 0x3F, R1"); #elif defined __GNUC__ AVR_ENTER_CRITICAL_REGION( ); 9d8: 2f b7 in r18, 0x3f ; 63 9da: 29 83 std Y+1, r18 ; 0x01 9dc: f8 94 cli volatile uint8_t * tmpAddr = address; #ifdef RAMPZ RAMPZ = 0; 9de: 1b be out 0x3b, r1 ; 59 #endif asm volatile( 9e0: fc 01 movw r30, r24 9e2: 08 ed ldi r16, 0xD8 ; 216 9e4: 04 bf out 0x34, r16 ; 52 9e6: 60 83 st Z, r22 : : "r" (tmpAddr), "r" (value), "M" (CCP_IOREG_gc), "i" (&CCP) : "r16", "r30", "r31" ); AVR_LEAVE_CRITICAL_REGION( ); 9e8: 89 81 ldd r24, Y+1 ; 0x01 9ea: 8f bf out 0x3f, r24 ; 63 #endif } 9ec: 0f 90 pop r0 9ee: cf 91 pop r28 9f0: df 91 pop r29 9f2: 0f 91 pop r16 9f4: 08 95 ret 000009f6 : */ void CLKSYS_XOSC_Config( OSC_FRQRANGE_t freqRange, bool lowPower32kHz, OSC_XOSCSEL_t xoscModeSelection ) { OSC.XOSCCTRL = (uint8_t) freqRange | 9f6: 66 23 and r22, r22 9f8: 11 f4 brne .+4 ; 0x9fe 9fa: 90 e0 ldi r25, 0x00 ; 0 9fc: 01 c0 rjmp .+2 ; 0xa00 9fe: 90 e2 ldi r25, 0x20 ; 32 a00: 48 2b or r20, r24 a02: 94 2b or r25, r20 a04: e0 e5 ldi r30, 0x50 ; 80 a06: f0 e0 ldi r31, 0x00 ; 0 a08: 92 83 std Z+2, r25 ; 0x02 ( lowPower32kHz ? OSC_X32KLPM_bm : 0 ) | xoscModeSelection; } a0a: 08 95 ret 00000a0c : * from 1 to 31, inclusive. */ void CLKSYS_PLL_Config( OSC_PLLSRC_t clockSource, uint8_t factor ) { factor &= OSC_PLLFAC_gm; OSC.PLLCTRL = (uint8_t) clockSource | ( factor << OSC_PLLFAC_gp ); a0c: 6f 71 andi r22, 0x1F ; 31 a0e: 68 2b or r22, r24 a10: e0 e5 ldi r30, 0x50 ; 80 a12: f0 e0 ldi r31, 0x00 ; 0 a14: 65 83 std Z+5, r22 ; 0x05 } a16: 08 95 ret 00000a18 : * * \return Non-zero if oscillator was disabled successfully. */ uint8_t CLKSYS_Disable( uint8_t oscSel ) { OSC.CTRL &= ~oscSel; a18: e0 e5 ldi r30, 0x50 ; 80 a1a: f0 e0 ldi r31, 0x00 ; 0 a1c: 20 81 ld r18, Z a1e: 98 2f mov r25, r24 a20: 90 95 com r25 a22: 92 23 and r25, r18 a24: 90 83 st Z, r25 uint8_t clkEnabled = OSC.CTRL & oscSel; a26: 90 81 ld r25, Z return clkEnabled; } a28: 89 23 and r24, r25 a2a: 08 95 ret 00000a2c : * \param PSBCfactor Prescaler B and C division factor, in the combination * of (1,1), (1,2), (4,1) or (2,2). */ void CLKSYS_Prescalers_Config( CLK_PSADIV_t PSAfactor, CLK_PSBCDIV_t PSBCfactor ) { a2c: 0f 93 push r16 a2e: df 93 push r29 a30: cf 93 push r28 a32: 0f 92 push r0 a34: cd b7 in r28, 0x3d ; 61 a36: de b7 in r29, 0x3e ; 62 // Restore global interrupt setting from scratch register. asm("out 0x3F, R1"); #elif defined __GNUC__ AVR_ENTER_CRITICAL_REGION( ); a38: 9f b7 in r25, 0x3f ; 63 a3a: 99 83 std Y+1, r25 ; 0x01 a3c: f8 94 cli volatile uint8_t * tmpAddr = address; #ifdef RAMPZ RAMPZ = 0; a3e: 1b be out 0x3b, r1 ; 59 #endif asm volatile( a40: 68 2b or r22, r24 a42: 81 e4 ldi r24, 0x41 ; 65 a44: 90 e0 ldi r25, 0x00 ; 0 a46: fc 01 movw r30, r24 a48: 08 ed ldi r16, 0xD8 ; 216 a4a: 04 bf out 0x34, r16 ; 52 a4c: 60 83 st Z, r22 : : "r" (tmpAddr), "r" (value), "M" (CCP_IOREG_gc), "i" (&CCP) : "r16", "r30", "r31" ); AVR_LEAVE_CRITICAL_REGION( ); a4e: 89 81 ldd r24, Y+1 ; 0x01 a50: 8f bf out 0x3f, r24 ; 63 void CLKSYS_Prescalers_Config( CLK_PSADIV_t PSAfactor, CLK_PSBCDIV_t PSBCfactor ) { uint8_t PSconfig = (uint8_t) PSAfactor | PSBCfactor; CCPWrite( &CLK.PSCTRL, PSconfig ); } a52: 0f 90 pop r0 a54: cf 91 pop r28 a56: df 91 pop r29 a58: 0f 91 pop r16 a5a: 08 95 ret 00000a5c : * prescaler block. * * \return Non-zero if change was successful. */ uint8_t CLKSYS_Main_ClockSource_Select( CLK_SCLKSEL_t clockSource ) { a5c: 0f 93 push r16 a5e: df 93 push r29 a60: cf 93 push r28 a62: 0f 92 push r0 a64: cd b7 in r28, 0x3d ; 61 a66: de b7 in r29, 0x3e ; 62 uint8_t clkCtrl = ( CLK.CTRL & ~CLK_SCLKSEL_gm ) | clockSource; a68: 20 91 40 00 lds r18, 0x0040 // Restore global interrupt setting from scratch register. asm("out 0x3F, R1"); #elif defined __GNUC__ AVR_ENTER_CRITICAL_REGION( ); a6c: 9f b7 in r25, 0x3f ; 63 a6e: 99 83 std Y+1, r25 ; 0x01 a70: f8 94 cli volatile uint8_t * tmpAddr = address; #ifdef RAMPZ RAMPZ = 0; a72: 1b be out 0x3b, r1 ; 59 #endif asm volatile( a74: a0 e4 ldi r26, 0x40 ; 64 a76: b0 e0 ldi r27, 0x00 ; 0 a78: 28 7f andi r18, 0xF8 ; 248 a7a: 28 2b or r18, r24 a7c: fd 01 movw r30, r26 a7e: 08 ed ldi r16, 0xD8 ; 216 a80: 04 bf out 0x34, r16 ; 52 a82: 20 83 st Z, r18 : : "r" (tmpAddr), "r" (value), "M" (CCP_IOREG_gc), "i" (&CCP) : "r16", "r30", "r31" ); AVR_LEAVE_CRITICAL_REGION( ); a84: 99 81 ldd r25, Y+1 ; 0x01 a86: 9f bf out 0x3f, r25 ; 63 */ uint8_t CLKSYS_Main_ClockSource_Select( CLK_SCLKSEL_t clockSource ) { uint8_t clkCtrl = ( CLK.CTRL & ~CLK_SCLKSEL_gm ) | clockSource; CCPWrite( &CLK.CTRL, clkCtrl ); clkCtrl = ( CLK.CTRL & clockSource ); a88: 9c 91 ld r25, X return clkCtrl; } a8a: 89 23 and r24, r25 a8c: 0f 90 pop r0 a8e: cf 91 pop r28 a90: df 91 pop r29 a92: 0f 91 pop r16 a94: 08 95 ret 00000a96 : * * \param clockSource Clock source to use for the RTC. */ void CLKSYS_RTC_ClockSource_Enable( CLK_RTCSRC_t clockSource ) { CLK.RTCCTRL = ( CLK.RTCCTRL & ~CLK_RTCSRC_gm ) | a96: e0 e4 ldi r30, 0x40 ; 64 a98: f0 e0 ldi r31, 0x00 ; 0 a9a: 93 81 ldd r25, Z+3 ; 0x03 a9c: 91 7f andi r25, 0xF1 ; 241 a9e: 91 60 ori r25, 0x01 ; 1 aa0: 98 2b or r25, r24 aa2: 93 83 std Z+3, r25 ; 0x03 clockSource | CLK_RTCEN_bm; } aa4: 08 95 ret 00000aa6 : * \param clkSource Clock source to calibrate, either OSC_RC2MCREF_bm or * OSC_RC32MCREF_bm. * \param extReference True if external crystal should be used as reference. */ void CLKSYS_AutoCalibration_Enable( uint8_t clkSource, bool extReference ) { aa6: 28 2f mov r18, r24 OSC.DFLLCTRL = ( OSC.DFLLCTRL & ~clkSource ) | aa8: 30 91 56 00 lds r19, 0x0056 aac: 66 23 and r22, r22 aae: 11 f0 breq .+4 ; 0xab4 ab0: 98 2f mov r25, r24 ab2: 01 c0 rjmp .+2 ; 0xab6 ab4: 90 e0 ldi r25, 0x00 ; 0 ab6: 82 2f mov r24, r18 ab8: 80 95 com r24 aba: 83 23 and r24, r19 abc: 98 2b or r25, r24 abe: e0 e5 ldi r30, 0x50 ; 80 ac0: f0 e0 ldi r31, 0x00 ; 0 ac2: 96 83 std Z+6, r25 ; 0x06 ( extReference ? clkSource : 0 ); if (clkSource == OSC_RC2MCREF_bm) { ac4: 21 30 cpi r18, 0x01 ; 1 ac6: 31 f4 brne .+12 ; 0xad4 DFLLRC2M.CTRL |= DFLL_ENABLE_bm; ac8: 80 91 68 00 lds r24, 0x0068 acc: 81 60 ori r24, 0x01 ; 1 ace: 80 93 68 00 sts 0x0068, r24 ad2: 08 95 ret } else if (clkSource == OSC_RC32MCREF_bm) { ad4: 22 30 cpi r18, 0x02 ; 2 ad6: 29 f4 brne .+10 ; 0xae2 DFLLRC32M.CTRL |= DFLL_ENABLE_bm; ad8: 80 91 60 00 lds r24, 0x0060 adc: 81 60 ori r24, 0x01 ; 1 ade: 80 93 60 00 sts 0x0060, r24 ae2: 08 95 ret 00000ae4 : * XOSCFD _will_ issue the XOSCF Non-maskable Interrupt (NMI) regardless of * any interrupt priorities and settings. Therefore, make sure that a handler * is implemented for the XOSCF NMI when you enable it. */ void CLKSYS_XOSC_FailureDetection_Enable( void ) { ae4: 0f 93 push r16 ae6: df 93 push r29 ae8: cf 93 push r28 aea: 0f 92 push r0 aec: cd b7 in r28, 0x3d ; 61 aee: de b7 in r29, 0x3e ; 62 // Restore global interrupt setting from scratch register. asm("out 0x3F, R1"); #elif defined __GNUC__ AVR_ENTER_CRITICAL_REGION( ); af0: 8f b7 in r24, 0x3f ; 63 af2: 89 83 std Y+1, r24 ; 0x01 af4: f8 94 cli volatile uint8_t * tmpAddr = address; #ifdef RAMPZ RAMPZ = 0; af6: 1b be out 0x3b, r1 ; 59 #endif asm volatile( af8: 23 e0 ldi r18, 0x03 ; 3 afa: 83 e5 ldi r24, 0x53 ; 83 afc: 90 e0 ldi r25, 0x00 ; 0 afe: fc 01 movw r30, r24 b00: 08 ed ldi r16, 0xD8 ; 216 b02: 04 bf out 0x34, r16 ; 52 b04: 20 83 st Z, r18 : : "r" (tmpAddr), "r" (value), "M" (CCP_IOREG_gc), "i" (&CCP) : "r16", "r30", "r31" ); AVR_LEAVE_CRITICAL_REGION( ); b06: 89 81 ldd r24, Y+1 ; 0x01 b08: 8f bf out 0x3f, r24 ; 63 * is implemented for the XOSCF NMI when you enable it. */ void CLKSYS_XOSC_FailureDetection_Enable( void ) { CCPWrite( &OSC.XOSCFAIL, ( OSC_XOSCFDIF_bm | OSC_XOSCFDEN_bm ) ); } b0a: 0f 90 pop r0 b0c: cf 91 pop r28 b0e: df 91 pop r29 b10: 0f 91 pop r16 b12: 08 95 ret 00000b14 : * This will lock the configuration until the next reset, or until the * External Oscillator Failure Detections (XOSCFD) feature detects a failure * and switches to internal 2MHz RC oscillator. */ void CLKSYS_Configuration_Lock( void ) { b14: 0f 93 push r16 b16: df 93 push r29 b18: cf 93 push r28 b1a: 0f 92 push r0 b1c: cd b7 in r28, 0x3d ; 61 b1e: de b7 in r29, 0x3e ; 62 // Restore global interrupt setting from scratch register. asm("out 0x3F, R1"); #elif defined __GNUC__ AVR_ENTER_CRITICAL_REGION( ); b20: 8f b7 in r24, 0x3f ; 63 b22: 89 83 std Y+1, r24 ; 0x01 b24: f8 94 cli volatile uint8_t * tmpAddr = address; #ifdef RAMPZ RAMPZ = 0; b26: 1b be out 0x3b, r1 ; 59 #endif asm volatile( b28: 21 e0 ldi r18, 0x01 ; 1 b2a: 82 e4 ldi r24, 0x42 ; 66 b2c: 90 e0 ldi r25, 0x00 ; 0 b2e: fc 01 movw r30, r24 b30: 08 ed ldi r16, 0xD8 ; 216 b32: 04 bf out 0x34, r16 ; 52 b34: 20 83 st Z, r18 : : "r" (tmpAddr), "r" (value), "M" (CCP_IOREG_gc), "i" (&CCP) : "r16", "r30", "r31" ); AVR_LEAVE_CRITICAL_REGION( ); b36: 89 81 ldd r24, Y+1 ; 0x01 b38: 8f bf out 0x3f, r24 ; 63 * and switches to internal 2MHz RC oscillator. */ void CLKSYS_Configuration_Lock( void ) { CCPWrite( &CLK.LOCK, CLK_LOCK_bm ); } b3a: 0f 90 pop r0 b3c: cf 91 pop r28 b3e: df 91 pop r29 b40: 0f 91 pop r16 b42: 08 95 ret 00000b44 : * * \param tc Timer/Counter module instance. * \param clockSelection Timer/Counter clock source setting. */ void TC0_ConfigClockSource( volatile TC0_t * tc, TC_CLKSEL_t clockSelection ) { b44: fc 01 movw r30, r24 tc->CTRLA = ( tc->CTRLA & ~TC0_CLKSEL_gm ) | clockSelection; b46: 80 81 ld r24, Z b48: 80 7f andi r24, 0xF0 ; 240 b4a: 86 2b or r24, r22 b4c: 80 83 st Z, r24 } b4e: 08 95 ret 00000b50 : * * \param tc Timer/Counter module instance. * \param clockSelection Timer/Counter clock source setting. */ void TC1_ConfigClockSource( volatile TC1_t * tc, TC_CLKSEL_t clockSelection ) { b50: fc 01 movw r30, r24 tc->CTRLA = ( tc->CTRLA & ~TC1_CLKSEL_gm ) | clockSelection; b52: 80 81 ld r24, Z b54: 80 7f andi r24, 0xF0 ; 240 b56: 86 2b or r24, r22 b58: 80 83 st Z, r24 } b5a: 08 95 ret 00000b5c : * * \param tc Timer/Counter module instance. * \param wgm Waveform generation mode. */ void TC0_ConfigWGM( volatile TC0_t * tc, TC_WGMODE_t wgm ) { b5c: fc 01 movw r30, r24 tc->CTRLB = ( tc->CTRLB & ~TC0_WGMODE_gm ) | wgm; b5e: 81 81 ldd r24, Z+1 ; 0x01 b60: 88 7f andi r24, 0xF8 ; 248 b62: 86 2b or r24, r22 b64: 81 83 std Z+1, r24 ; 0x01 } b66: 08 95 ret 00000b68 : * * \param tc Timer/Counter module instance. * \param wgm Waveform generation mode. */ void TC1_ConfigWGM( volatile TC1_t * tc, TC_WGMODE_t wgm ) { b68: fc 01 movw r30, r24 tc->CTRLB = ( tc->CTRLB & ~TC1_WGMODE_gm ) | wgm; b6a: 81 81 ldd r24, Z+1 ; 0x01 b6c: 88 7f andi r24, 0xF8 ; 248 b6e: 86 2b or r24, r22 b70: 81 83 std Z+1, r24 ; 0x01 } b72: 08 95 ret 00000b74 : * * \param tc Timer/Counter module instance. * \param eventSource Event source selection. */ void TC0_ConfigInputCapture( volatile TC0_t * tc, TC_EVSEL_t eventSource ) { b74: fc 01 movw r30, r24 tc->CTRLD = ( tc->CTRLD & ~( TC0_EVSEL_gm | TC0_EVACT_gm ) ) | b76: 83 81 ldd r24, Z+3 ; 0x03 b78: 80 71 andi r24, 0x10 ; 16 b7a: 80 62 ori r24, 0x20 ; 32 b7c: 86 2b or r24, r22 b7e: 83 83 std Z+3, r24 ; 0x03 eventSource | TC_EVACT_CAPT_gc; } b80: 08 95 ret 00000b82 : * * \param tc Timer/Counter module instance. * \param eventSource Event source selection. */ void TC1_ConfigInputCapture( volatile TC1_t * tc, TC_EVSEL_t eventSource ) { b82: fc 01 movw r30, r24 tc->CTRLD = ( tc->CTRLD & ~( TC1_EVSEL_gm | TC1_EVACT_gm ) ) | b84: 83 81 ldd r24, Z+3 ; 0x03 b86: 80 71 andi r24, 0x10 ; 16 b88: 80 62 ori r24, 0x20 ; 32 b8a: 86 2b or r24, r22 b8c: 83 83 std Z+3, r24 ; 0x03 eventSource | TC_EVACT_CAPT_gc; } b8e: 08 95 ret 00000b90 : * * \param tc Timer/Counter module instance. * \param enableMask Mask of channels to enable. */ void TC0_EnableCCChannels( volatile TC0_t * tc, uint8_t enableMask ) { b90: fc 01 movw r30, r24 /* Make sure only CCxEN bits are set in enableMask. */ enableMask &= ( TC0_CCAEN_bm | TC0_CCBEN_bm | TC0_CCCEN_bm | TC0_CCDEN_bm ); /* Enable channels. */ tc->CTRLB |= enableMask; b92: 81 81 ldd r24, Z+1 ; 0x01 b94: 60 7f andi r22, 0xF0 ; 240 b96: 86 2b or r24, r22 b98: 81 83 std Z+1, r24 ; 0x01 } b9a: 08 95 ret 00000b9c : * * \param tc Timer/Counter module instance. * \param enableMask Mask of channels to enable. */ void TC1_EnableCCChannels( volatile TC1_t * tc, uint8_t enableMask ) { b9c: fc 01 movw r30, r24 /* Make sure only CCxEN bits are set in enableMask. */ enableMask &= ( TC1_CCAEN_bm | TC1_CCBEN_bm ); /* Enable channels. */ tc->CTRLB |= enableMask; b9e: 81 81 ldd r24, Z+1 ; 0x01 ba0: 60 73 andi r22, 0x30 ; 48 ba2: 86 2b or r24, r22 ba4: 81 83 std Z+1, r24 ; 0x01 } ba6: 08 95 ret 00000ba8 : * * \param tc Timer/Counter module instance. * \param disableMask Mask of channels to disable. */ void TC0_DisableCCChannels( volatile TC0_t * tc, uint8_t disableMask ) { ba8: fc 01 movw r30, r24 /* Make sure only CCxEN bits are set in disableMask. */ disableMask &= ( TC0_CCAEN_bm | TC0_CCBEN_bm | TC0_CCCEN_bm | TC0_CCDEN_bm ); /* Disable channels. */ tc->CTRLB &= ~disableMask; baa: 81 81 ldd r24, Z+1 ; 0x01 bac: 60 7f andi r22, 0xF0 ; 240 bae: 60 95 com r22 bb0: 86 23 and r24, r22 bb2: 81 83 std Z+1, r24 ; 0x01 } bb4: 08 95 ret 00000bb6 : * * \param tc Timer/Counter module instance. * \param disableMask Mask of channels to disable. */ void TC1_DisableCCChannels( volatile TC1_t * tc, uint8_t disableMask ) { bb6: fc 01 movw r30, r24 /* Make sure only CCxEN bits are set in disableMask. */ disableMask &= ( TC1_CCAEN_bm | TC1_CCBEN_bm ); /* Disable channels. */ tc->CTRLB &= ~disableMask; bb8: 81 81 ldd r24, Z+1 ; 0x01 bba: 60 73 andi r22, 0x30 ; 48 bbc: 60 95 com r22 bbe: 86 23 and r24, r22 bc0: 81 83 std Z+1, r24 ; 0x01 } bc2: 08 95 ret 00000bc4 : * * \param tc Timer/Counter module instance. * \param intLevel New overflow interrupt level. */ void TC0_SetOverflowIntLevel( volatile TC0_t * tc, TC_OVFINTLVL_t intLevel ) { bc4: fc 01 movw r30, r24 tc->INTCTRLA = ( tc->INTCTRLA & ~TC0_OVFINTLVL_gm ) | intLevel; bc6: 86 81 ldd r24, Z+6 ; 0x06 bc8: 8c 7f andi r24, 0xFC ; 252 bca: 86 2b or r24, r22 bcc: 86 83 std Z+6, r24 ; 0x06 } bce: 08 95 ret 00000bd0 : * * \param tc Timer/Counter module instance. * \param intLevel New overflow interrupt level. */ void TC1_SetOverflowIntLevel( volatile TC1_t * tc, TC_OVFINTLVL_t intLevel ) { bd0: fc 01 movw r30, r24 tc->INTCTRLA = ( tc->INTCTRLA & ~TC1_OVFINTLVL_gm ) | intLevel; bd2: 86 81 ldd r24, Z+6 ; 0x06 bd4: 8c 7f andi r24, 0xFC ; 252 bd6: 86 2b or r24, r22 bd8: 86 83 std Z+6, r24 ; 0x06 } bda: 08 95 ret 00000bdc : * * \param tc Timer/Counter module instance. * \param intLevel New error interrupt level. */ void TC0_SetErrorIntLevel( volatile TC0_t * tc, TC_ERRINTLVL_t intLevel ) { bdc: fc 01 movw r30, r24 tc->INTCTRLA = ( tc->INTCTRLA & ~TC0_ERRINTLVL_gm ) | intLevel; bde: 86 81 ldd r24, Z+6 ; 0x06 be0: 83 7f andi r24, 0xF3 ; 243 be2: 86 2b or r24, r22 be4: 86 83 std Z+6, r24 ; 0x06 } be6: 08 95 ret 00000be8 : * * \param tc Timer/Counter module instance. * \param intLevel New error interrupt level. */ void TC1_SetErrorIntLevel( volatile TC1_t * tc, TC_ERRINTLVL_t intLevel ) { be8: fc 01 movw r30, r24 tc->INTCTRLA = ( tc->INTCTRLA & ~TC1_ERRINTLVL_gm ) | intLevel; bea: 86 81 ldd r24, Z+6 ; 0x06 bec: 83 7f andi r24, 0xF3 ; 243 bee: 86 2b or r24, r22 bf0: 86 83 std Z+6, r24 ; 0x06 } bf2: 08 95 ret 00000bf4 : * * \param tc Timer/Counter module instance. * \param intLevel New compare/capture channel A interrupt level. */ void TC0_SetCCAIntLevel( volatile TC0_t * tc, TC_CCAINTLVL_t intLevel ) { bf4: fc 01 movw r30, r24 tc->INTCTRLB = ( tc->INTCTRLB & ~TC0_CCAINTLVL_gm ) | intLevel; bf6: 87 81 ldd r24, Z+7 ; 0x07 bf8: 8c 7f andi r24, 0xFC ; 252 bfa: 86 2b or r24, r22 bfc: 87 83 std Z+7, r24 ; 0x07 } bfe: 08 95 ret 00000c00 : * * \param tc Timer/Counter module instance. * \param intLevel New compare/capture channel A interrupt level. */ void TC1_SetCCAIntLevel( volatile TC1_t * tc, TC_CCAINTLVL_t intLevel ) { c00: fc 01 movw r30, r24 tc->INTCTRLB = ( tc->INTCTRLB & ~TC1_CCAINTLVL_gm ) | intLevel; c02: 87 81 ldd r24, Z+7 ; 0x07 c04: 8c 7f andi r24, 0xFC ; 252 c06: 86 2b or r24, r22 c08: 87 83 std Z+7, r24 ; 0x07 } c0a: 08 95 ret 00000c0c : * * \param tc Timer/Counter module instance. * \param intLevel New compare/capture channel B interrupt level. */ void TC0_SetCCBIntLevel( volatile TC0_t * tc, TC_CCBINTLVL_t intLevel ) { c0c: fc 01 movw r30, r24 tc->INTCTRLB = ( tc->INTCTRLB & ~TC0_CCBINTLVL_gm ) | intLevel; c0e: 87 81 ldd r24, Z+7 ; 0x07 c10: 83 7f andi r24, 0xF3 ; 243 c12: 86 2b or r24, r22 c14: 87 83 std Z+7, r24 ; 0x07 } c16: 08 95 ret 00000c18 : * * \param tc Timer/Counter module instance. * \param intLevel New compare/capture channel B interrupt level. */ void TC1_SetCCBIntLevel( volatile TC1_t * tc, TC_CCBINTLVL_t intLevel ) { c18: fc 01 movw r30, r24 tc->INTCTRLB = ( tc->INTCTRLB & ~TC1_CCBINTLVL_gm ) | intLevel; c1a: 87 81 ldd r24, Z+7 ; 0x07 c1c: 83 7f andi r24, 0xF3 ; 243 c1e: 86 2b or r24, r22 c20: 87 83 std Z+7, r24 ; 0x07 } c22: 08 95 ret 00000c24 : * * \param tc Timer/Counter module instance. * \param intLevel New compare/capture channel A interrupt level. */ void TC0_SetCCCIntLevel( volatile TC0_t * tc, TC_CCCINTLVL_t intLevel ) { c24: fc 01 movw r30, r24 tc->INTCTRLB = ( tc->INTCTRLB & ~TC0_CCCINTLVL_gm ) | intLevel; c26: 87 81 ldd r24, Z+7 ; 0x07 c28: 8f 7c andi r24, 0xCF ; 207 c2a: 86 2b or r24, r22 c2c: 87 83 std Z+7, r24 ; 0x07 } c2e: 08 95 ret 00000c30 : * * \param tc Timer/Counter module instance. * \param intLevel New compare/capture channel A interrupt level. */ void TC0_SetCCDIntLevel( volatile TC0_t * tc, TC_CCDINTLVL_t intLevel ) { c30: fc 01 movw r30, r24 tc->INTCTRLB = ( tc->INTCTRLB & ~TC0_CCDINTLVL_gm ) | intLevel; c32: 87 81 ldd r24, Z+7 ; 0x07 c34: 8f 73 andi r24, 0x3F ; 63 c36: 86 2b or r24, r22 c38: 87 83 std Z+7, r24 ; 0x07 } c3a: 08 95 ret 00000c3c : * reset of the device. * * \param tc Timer/Counter 0 module instance. */ void TC0_Reset( volatile TC0_t * tc ) { c3c: fc 01 movw r30, r24 /* TC must be turned off before a Reset command. */ tc->CTRLA = ( tc->CTRLA & ~TC0_CLKSEL_gm ) | TC_CLKSEL_OFF_gc; c3e: 80 81 ld r24, Z c40: 80 7f andi r24, 0xF0 ; 240 c42: 80 83 st Z, r24 /* Issue Reset command. */ tc->CTRLFSET = TC_CMD_RESET_gc; c44: 8c e0 ldi r24, 0x0C ; 12 c46: 81 87 std Z+9, r24 ; 0x09 } c48: 08 95 ret 00000c4a : * reset of the device. * * \param tc Timer/Counter 1 module instance. */ void TC1_Reset( volatile TC1_t * tc ) { c4a: fc 01 movw r30, r24 /* TC must be turned off before a Reset command. */ tc->CTRLA = ( tc->CTRLA & ~TC1_CLKSEL_gm ) | TC_CLKSEL_OFF_gc; c4c: 80 81 ld r24, Z c4e: 80 7f andi r24, 0xF0 ; 240 c50: 80 83 st Z, r24 /* Issue Reset command. */ tc->CTRLFSET = TC_CMD_RESET_gc; c52: 8c e0 ldi r24, 0x0C ; 12 c54: 81 87 std Z+9, r24 ; 0x09 } c56: 08 95 ret 00000c58 <_exit>: c58: f8 94 cli 00000c5a <__stop_program>: c5a: ff cf rjmp .-2 ; 0xc5a <__stop_program>