spi_test_two.elf: file format elf32-avr Sections: Idx Name Size VMA LMA File off Algn 0 .text 00000c46 00000000 00000000 00000094 2**1 CONTENTS, ALLOC, LOAD, READONLY, CODE 1 .data 00000008 00802000 00000c46 00000cda 2**0 CONTENTS, ALLOC, LOAD, DATA 2 .bss 00000042 00802008 00802008 00000ce2 2**0 ALLOC 3 .debug_aranges 00000080 00000000 00000000 00000ce2 2**0 CONTENTS, READONLY, DEBUGGING 4 .debug_pubnames 00000558 00000000 00000000 00000d62 2**0 CONTENTS, READONLY, DEBUGGING 5 .debug_info 00002eb9 00000000 00000000 000012ba 2**0 CONTENTS, READONLY, DEBUGGING 6 .debug_abbrev 00000803 00000000 00000000 00004173 2**0 CONTENTS, READONLY, DEBUGGING 7 .debug_line 00000e2c 00000000 00000000 00004976 2**0 CONTENTS, READONLY, DEBUGGING 8 .debug_frame 00000360 00000000 00000000 000057a4 2**2 CONTENTS, READONLY, DEBUGGING 9 .debug_str 00001707 00000000 00000000 00005b04 2**0 CONTENTS, READONLY, DEBUGGING 10 .debug_loc 00000769 00000000 00000000 0000720b 2**0 CONTENTS, READONLY, DEBUGGING 11 .debug_ranges 00000018 00000000 00000000 00007974 2**0 CONTENTS, READONLY, DEBUGGING Disassembly of section .text: 00000000 <__vectors>: 0: 0c 94 fa 00 jmp 0x1f4 ; 0x1f4 <__ctors_end> 4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 10: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 14: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 18: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 20: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 24: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 28: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 2c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 30: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 34: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 38: 0c 94 bf 02 jmp 0x57e ; 0x57e <__vector_14> 3c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 40: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 44: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 48: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 4c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 50: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 54: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 58: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 5c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 60: 0c 94 9f 02 jmp 0x53e ; 0x53e <__vector_24> 64: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 68: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 6c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 70: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 74: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 78: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 7c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 80: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 84: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 88: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 8c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 90: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 94: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 98: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 9c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> a0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> a4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> a8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> ac: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> b0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> b4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> b8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> bc: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> c0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> c4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> c8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> cc: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> d0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> d4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> d8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> dc: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> e0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> e4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> e8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> ec: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> f0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> f4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> f8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> fc: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 100: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 104: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 108: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 10c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 110: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 114: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 118: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 11c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 120: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 124: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 128: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 12c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 130: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 134: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 138: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 13c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 140: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 144: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 148: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 14c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 150: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 154: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 158: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 15c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 160: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 164: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 168: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 16c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 170: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 174: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 178: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 17c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 180: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 184: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 188: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 18c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 190: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 194: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 198: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 19c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1a0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1a4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1a8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1ac: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1b0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1b4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1b8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1bc: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1c0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1c4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1c8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1cc: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1d0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1d4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1d8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1dc: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1e0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1e4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1e8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1ec: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1f0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 000001f4 <__ctors_end>: 1f4: 11 24 eor r1, r1 1f6: 1f be out 0x3f, r1 ; 63 1f8: cf ef ldi r28, 0xFF ; 255 1fa: df e3 ldi r29, 0x3F ; 63 1fc: de bf out 0x3e, r29 ; 62 1fe: cd bf out 0x3d, r28 ; 61 200: 00 e0 ldi r16, 0x00 ; 0 202: 0c bf out 0x3c, r16 ; 60 204: 18 be out 0x38, r1 ; 56 206: 19 be out 0x39, r1 ; 57 208: 1a be out 0x3a, r1 ; 58 20a: 1b be out 0x3b, r1 ; 59 0000020c <__do_copy_data>: 20c: 10 e2 ldi r17, 0x20 ; 32 20e: a0 e0 ldi r26, 0x00 ; 0 210: b0 e2 ldi r27, 0x20 ; 32 212: e6 e4 ldi r30, 0x46 ; 70 214: fc e0 ldi r31, 0x0C ; 12 216: 00 e0 ldi r16, 0x00 ; 0 218: 0b bf out 0x3b, r16 ; 59 21a: 02 c0 rjmp .+4 ; 0x220 <__do_copy_data+0x14> 21c: 07 90 elpm r0, Z+ 21e: 0d 92 st X+, r0 220: a8 30 cpi r26, 0x08 ; 8 222: b1 07 cpc r27, r17 224: d9 f7 brne .-10 ; 0x21c <__do_copy_data+0x10> 226: 1b be out 0x3b, r1 ; 59 00000228 <__do_clear_bss>: 228: 10 e2 ldi r17, 0x20 ; 32 22a: a8 e0 ldi r26, 0x08 ; 8 22c: b0 e2 ldi r27, 0x20 ; 32 22e: 01 c0 rjmp .+2 ; 0x232 <.do_clear_bss_start> 00000230 <.do_clear_bss_loop>: 230: 1d 92 st X+, r1 00000232 <.do_clear_bss_start>: 232: aa 34 cpi r26, 0x4A ; 74 234: b1 07 cpc r27, r17 236: e1 f7 brne .-8 ; 0x230 <.do_clear_bss_loop> 238: 0e 94 2c 03 call 0x658 ; 0x658
23c: 0c 94 21 06 jmp 0xc42 ; 0xc42 <_exit> 00000240 <__bad_interrupt>: 240: 0c 94 00 00 jmp 0 ; 0x0 <__vectors> 00000244 : Set up Timer/Counter 0 to work from CPICLK/64 with period of 31500 (a frequency of about 1 Hz) and enable overflow interrupt note: Initializing this timere will instantiate a heartbeat by nature of the interrupt linked to it */ TCC0.PER = 31650; 244: e0 e0 ldi r30, 0x00 ; 0 246: f8 e0 ldi r31, 0x08 ; 8 248: 82 ea ldi r24, 0xA2 ; 162 24a: 9b e7 ldi r25, 0x7B ; 123 24c: 86 a3 std Z+38, r24 ; 0x26 24e: 97 a3 std Z+39, r25 ; 0x27 TCC0.CTRLA = (TCC0.CTRLA & ~TC0_CLKSEL_gm) | TC_CLKSEL_DIV1024_gc; 250: 80 81 ld r24, Z 252: 80 7f andi r24, 0xF0 ; 240 254: 87 60 ori r24, 0x07 ; 7 256: 80 83 st Z, r24 TCC0.INTCTRLA = (TCC0.INTCTRLA & ~TC0_OVFINTLVL_gm) | 258: 86 81 ldd r24, Z+6 ; 0x06 25a: 8c 7f andi r24, 0xFC ; 252 25c: 82 60 ori r24, 0x02 ; 2 25e: 86 83 std Z+6, r24 ; 0x06 TC_OVFINTLVL_MED_gc; PMIC.CTRL |= PMIC_MEDLVLEN_bm; 260: e0 ea ldi r30, 0xA0 ; 160 262: f0 e0 ldi r31, 0x00 ; 0 264: 82 81 ldd r24, Z+2 ; 0x02 266: 82 60 ori r24, 0x02 ; 2 268: 82 83 std Z+2, r24 ; 0x02 } 26a: 08 95 ret 0000026c : /* --------------------------------------------------------------- */ void Process_SPI(void){ /* If the spi interrupt is fired do things */ if (spi->int_flag ==1 ){ 26c: a0 91 02 20 lds r26, 0x2002 270: b0 91 03 20 lds r27, 0x2003 274: 8c 91 ld r24, X 276: 81 30 cpi r24, 0x01 ; 1 278: 09 f0 breq .+2 ; 0x27c 27a: b3 c0 rjmp .+358 ; 0x3e2 uint8_t send_byte = 0x00; uint8_t receive_byte = 0x00; /* Transmit */ /* ------------------------------------------------------ */ if (spi->tx_flag == 0){ 27c: 12 96 adiw r26, 0x02 ; 2 27e: 8c 91 ld r24, X 280: 12 97 sbiw r26, 0x02 ; 2 282: 88 23 and r24, r24 284: 29 f4 brne .+10 ; 0x290 spi->tx_counter = 0; 286: 14 96 adiw r26, 0x04 ; 4 288: 1c 92 st X, r1 28a: 14 97 sbiw r26, 0x04 ; 4 28c: 20 e0 ldi r18, 0x00 ; 0 28e: 44 c0 rjmp .+136 ; 0x318 send_byte = 0x00; }else{ if (spi->tx_counter == (spi->tx_len+4)){ 290: 14 96 adiw r26, 0x04 ; 4 292: 2c 91 ld r18, X 294: 14 97 sbiw r26, 0x04 ; 4 296: 30 e0 ldi r19, 0x00 ; 0 298: 18 96 adiw r26, 0x08 ; 8 29a: 8c 91 ld r24, X 29c: 18 97 sbiw r26, 0x08 ; 8 29e: 90 e0 ldi r25, 0x00 ; 0 2a0: 04 96 adiw r24, 0x04 ; 4 2a2: 28 17 cp r18, r24 2a4: 39 07 cpc r19, r25 2a6: 19 f4 brne .+6 ; 0x2ae spi->tx_counter = 0; 2a8: 14 96 adiw r26, 0x04 ; 4 2aa: 1c 92 st X, r1 2ac: 14 97 sbiw r26, 0x04 ; 4 } if (spi->tx_counter == (spi->tx_len+3)){ 2ae: 14 96 adiw r26, 0x04 ; 4 2b0: 2c 91 ld r18, X 2b2: 14 97 sbiw r26, 0x04 ; 4 2b4: 30 e0 ldi r19, 0x00 ; 0 2b6: 18 96 adiw r26, 0x08 ; 8 2b8: 8c 91 ld r24, X 2ba: 18 97 sbiw r26, 0x08 ; 8 2bc: 90 e0 ldi r25, 0x00 ; 0 2be: 03 96 adiw r24, 0x03 ; 3 2c0: 28 17 cp r18, r24 2c2: 39 07 cpc r19, r25 2c4: 11 f0 breq .+4 ; 0x2ca 2c6: 20 e0 ldi r18, 0x00 ; 0 2c8: 04 c0 rjmp .+8 ; 0x2d2 send_byte = SPI_END_TOKEN; spi->tx_flag = 0; 2ca: 12 96 adiw r26, 0x02 ; 2 2cc: 1c 92 st X, r1 2ce: 12 97 sbiw r26, 0x02 ; 2 2d0: 24 e4 ldi r18, 0x44 ; 68 } if (spi->tx_counter<(spi->tx_len+3) && spi->tx_counter>0){ 2d2: 14 96 adiw r26, 0x04 ; 4 2d4: 3c 91 ld r19, X 2d6: 14 97 sbiw r26, 0x04 ; 4 2d8: e3 2f mov r30, r19 2da: f0 e0 ldi r31, 0x00 ; 0 2dc: 18 96 adiw r26, 0x08 ; 8 2de: 8c 91 ld r24, X 2e0: 18 97 sbiw r26, 0x08 ; 8 2e2: 90 e0 ldi r25, 0x00 ; 0 2e4: 02 96 adiw r24, 0x02 ; 2 2e6: 8e 17 cp r24, r30 2e8: 9f 07 cpc r25, r31 2ea: 4c f0 brlt .+18 ; 0x2fe 2ec: 33 23 and r19, r19 2ee: 39 f0 breq .+14 ; 0x2fe send_byte = spi->tx_buffer[(spi->tx_counter)-1]; 2f0: ea 0f add r30, r26 2f2: fb 1f adc r31, r27 2f4: 22 89 ldd r18, Z+18 ; 0x12 spi->tx_counter++; 2f6: 3f 5f subi r19, 0xFF ; 255 2f8: 14 96 adiw r26, 0x04 ; 4 2fa: 3c 93 st X, r19 2fc: 14 97 sbiw r26, 0x04 ; 4 } if (spi->tx_counter == 0){ 2fe: 14 96 adiw r26, 0x04 ; 4 300: 8c 91 ld r24, X 302: 14 97 sbiw r26, 0x04 ; 4 304: 88 23 and r24, r24 306: 41 f4 brne .+16 ; 0x318 send_byte = SPI_START_TOKEN | spi->tx_len; 308: 18 96 adiw r26, 0x08 ; 8 30a: 2c 91 ld r18, X 30c: 18 97 sbiw r26, 0x08 ; 8 30e: 20 6b ori r18, 0xB0 ; 176 spi->tx_counter++; 310: 81 e0 ldi r24, 0x01 ; 1 312: 14 96 adiw r26, 0x04 ; 4 314: 8c 93 st X, r24 316: 14 97 sbiw r26, 0x04 ; 4 /* ------------------------------------------------------ */ /* For PIC */ /*receive_byte = spi_xfer(send_byte);*/ /* For atxmega */ SPI_SlaveWriteByte(&spiSlaveC, send_byte); 318: e0 91 08 20 lds r30, 0x2008 31c: f0 91 09 20 lds r31, 0x2009 320: 23 83 std Z+3, r18 ; 0x03 receive_byte = SPI_SlaveReadByte(&spiSlaveC); 322: 43 81 ldd r20, Z+3 ; 0x03 /* ------------------------------------------------------ */ /* Receive */ if (spi->rx_counter == (spi->rx_len+4)){ 324: 13 96 adiw r26, 0x03 ; 3 326: 2c 91 ld r18, X 328: 13 97 sbiw r26, 0x03 ; 3 32a: 30 e0 ldi r19, 0x00 ; 0 32c: 17 96 adiw r26, 0x07 ; 7 32e: 8c 91 ld r24, X 330: 17 97 sbiw r26, 0x07 ; 7 332: 90 e0 ldi r25, 0x00 ; 0 334: 04 96 adiw r24, 0x04 ; 4 336: 28 17 cp r18, r24 338: 39 07 cpc r19, r25 33a: 19 f4 brne .+6 ; 0x342 spi->rx_counter = 0; 33c: 13 96 adiw r26, 0x03 ; 3 33e: 1c 92 st X, r1 340: 13 97 sbiw r26, 0x03 ; 3 } if (spi->rx_counter == (spi->rx_len+3)){ 342: 13 96 adiw r26, 0x03 ; 3 344: 2c 91 ld r18, X 346: 13 97 sbiw r26, 0x03 ; 3 348: 30 e0 ldi r19, 0x00 ; 0 34a: 17 96 adiw r26, 0x07 ; 7 34c: 8c 91 ld r24, X 34e: 17 97 sbiw r26, 0x07 ; 7 350: 90 e0 ldi r25, 0x00 ; 0 352: 03 96 adiw r24, 0x03 ; 3 354: 28 17 cp r18, r24 356: 39 07 cpc r19, r25 358: c1 f4 brne .+48 ; 0x38a if (receive_byte == SPI_END_TOKEN){ 35a: 44 34 cpi r20, 0x44 ; 68 35c: 99 f4 brne .+38 ; 0x384 PORTE.OUTTGL = PIN4_bm; 35e: 80 e1 ldi r24, 0x10 ; 16 360: e0 e8 ldi r30, 0x80 ; 128 362: f6 e0 ldi r31, 0x06 ; 6 364: 87 83 std Z+7, r24 ; 0x07 spi->first_message = 1; 366: 81 e0 ldi r24, 0x01 ; 1 368: 5d 96 adiw r26, 0x1d ; 29 36a: 8c 93 st X, r24 36c: 5d 97 sbiw r26, 0x1d ; 29 spi->rx_flag = 1; 36e: 11 96 adiw r26, 0x01 ; 1 370: 8c 93 st X, r24 372: 11 97 sbiw r26, 0x01 ; 1 spi->rx_counter++; 374: 13 96 adiw r26, 0x03 ; 3 376: 8c 91 ld r24, X 378: 13 97 sbiw r26, 0x03 ; 3 37a: 8f 5f subi r24, 0xFF ; 255 37c: 13 96 adiw r26, 0x03 ; 3 37e: 8c 93 st X, r24 380: 13 97 sbiw r26, 0x03 ; 3 382: 03 c0 rjmp .+6 ; 0x38a }else{ spi->rx_counter = 0; 384: 13 96 adiw r26, 0x03 ; 3 386: 1c 92 st X, r1 388: 13 97 sbiw r26, 0x03 ; 3 } } if (spi->rx_counter<(spi->rx_len+3) && spi->rx_counter>0){ 38a: 13 96 adiw r26, 0x03 ; 3 38c: 2c 91 ld r18, X 38e: 13 97 sbiw r26, 0x03 ; 3 390: e2 2f mov r30, r18 392: f0 e0 ldi r31, 0x00 ; 0 394: 17 96 adiw r26, 0x07 ; 7 396: 8c 91 ld r24, X 398: 17 97 sbiw r26, 0x07 ; 7 39a: 90 e0 ldi r25, 0x00 ; 0 39c: 02 96 adiw r24, 0x02 ; 2 39e: 8e 17 cp r24, r30 3a0: 9f 07 cpc r25, r31 3a2: 4c f0 brlt .+18 ; 0x3b6 3a4: 22 23 and r18, r18 3a6: 39 f0 breq .+14 ; 0x3b6 spi->rx_buffer[(spi->rx_counter)-1] = receive_byte; 3a8: ea 0f add r30, r26 3aa: fb 1f adc r31, r27 3ac: 40 87 std Z+8, r20 ; 0x08 spi->rx_counter++; 3ae: 2f 5f subi r18, 0xFF ; 255 3b0: 13 96 adiw r26, 0x03 ; 3 3b2: 2c 93 st X, r18 3b4: 13 97 sbiw r26, 0x03 ; 3 } if (spi->rx_counter == 0){ 3b6: 13 96 adiw r26, 0x03 ; 3 3b8: 8c 91 ld r24, X 3ba: 13 97 sbiw r26, 0x03 ; 3 3bc: 88 23 and r24, r24 3be: 81 f4 brne .+32 ; 0x3e0 if ((receive_byte & 0b11110000) == SPI_START_TOKEN){ 3c0: 84 2f mov r24, r20 3c2: 80 7f andi r24, 0xF0 ; 240 3c4: 80 3b cpi r24, 0xB0 ; 176 3c6: 49 f4 brne .+18 ; 0x3da spi->rx_len = (receive_byte & 0b00001111); 3c8: 4f 70 andi r20, 0x0F ; 15 3ca: 17 96 adiw r26, 0x07 ; 7 3cc: 4c 93 st X, r20 3ce: 17 97 sbiw r26, 0x07 ; 7 spi->rx_counter++; 3d0: 81 e0 ldi r24, 0x01 ; 1 3d2: 13 96 adiw r26, 0x03 ; 3 3d4: 8c 93 st X, r24 3d6: 13 97 sbiw r26, 0x03 ; 3 3d8: 03 c0 rjmp .+6 ; 0x3e0 }else{ spi->rx_counter = 0; 3da: 13 96 adiw r26, 0x03 ; 3 3dc: 1c 92 st X, r1 3de: 13 97 sbiw r26, 0x03 ; 3 } } /* ------------------------------------------------------ */ spi->int_flag = 0; 3e0: 1c 92 st X, r1 3e2: 08 95 ret 000003e4 : } return; } /* --------------------------------------------------------------- */ void Process_Buffers(void){ 3e4: cf 93 push r28 3e6: df 93 push r29 /* Priority is currently determined by the sequence of buffers in this function */ if (RB->tx_flag == 1){ 3e8: 20 91 04 20 lds r18, 0x2004 3ec: 30 91 05 20 lds r19, 0x2005 3f0: f9 01 movw r30, r18 3f2: 83 85 ldd r24, Z+11 ; 0x0b 3f4: 81 30 cpi r24, 0x01 ; 1 3f6: c9 f4 brne .+50 ; 0x42a spi->tx_len = RB->len; 3f8: c0 91 02 20 lds r28, 0x2002 3fc: d0 91 03 20 lds r29, 0x2003 400: 82 85 ldd r24, Z+10 ; 0x0a 402: 88 87 std Y+8, r24 ; 0x08 404: 40 e0 ldi r20, 0x00 ; 0 406: 08 c0 rjmp .+16 ; 0x418 for (uint8_t i=0;i<(spi->tx_len+2);i++){ spi->tx_buffer[i] = RB->buffer[i]; 408: fe 01 movw r30, r28 40a: ea 0f add r30, r26 40c: fb 1f adc r31, r27 40e: a2 0f add r26, r18 410: b3 1f adc r27, r19 412: 8c 91 ld r24, X 414: 83 8b std Z+19, r24 ; 0x13 in this function */ if (RB->tx_flag == 1){ spi->tx_len = RB->len; for (uint8_t i=0;i<(spi->tx_len+2);i++){ 416: 4f 5f subi r20, 0xFF ; 255 418: a4 2f mov r26, r20 41a: b0 e0 ldi r27, 0x00 ; 0 41c: 88 85 ldd r24, Y+8 ; 0x08 41e: 90 e0 ldi r25, 0x00 ; 0 420: 01 96 adiw r24, 0x01 ; 1 422: 8a 17 cp r24, r26 424: 9b 07 cpc r25, r27 426: 84 f7 brge .-32 ; 0x408 428: 20 c0 rjmp .+64 ; 0x46a spi->tx_buffer[i] = RB->buffer[i]; } RB->tx_flag = 0; spi->tx_flag = 1; }else if (echo->tx_flag == 1){ 42a: 20 91 06 20 lds r18, 0x2006 42e: 30 91 07 20 lds r19, 0x2007 432: f9 01 movw r30, r18 434: 83 85 ldd r24, Z+11 ; 0x0b 436: 81 30 cpi r24, 0x01 ; 1 438: e1 f4 brne .+56 ; 0x472 spi->tx_len = echo->len; 43a: c0 91 02 20 lds r28, 0x2002 43e: d0 91 03 20 lds r29, 0x2003 442: 82 85 ldd r24, Z+10 ; 0x0a 444: 88 87 std Y+8, r24 ; 0x08 446: 40 e0 ldi r20, 0x00 ; 0 448: 08 c0 rjmp .+16 ; 0x45a for (uint8_t i=0;i<(spi->tx_len+2);i++){ spi->tx_buffer[i] = echo->buffer[i]; 44a: fe 01 movw r30, r28 44c: ea 0f add r30, r26 44e: fb 1f adc r31, r27 450: a2 0f add r26, r18 452: b3 1f adc r27, r19 454: 8c 91 ld r24, X 456: 83 8b std Z+19, r24 ; 0x13 } RB->tx_flag = 0; spi->tx_flag = 1; }else if (echo->tx_flag == 1){ spi->tx_len = echo->len; for (uint8_t i=0;i<(spi->tx_len+2);i++){ 458: 4f 5f subi r20, 0xFF ; 255 45a: a4 2f mov r26, r20 45c: b0 e0 ldi r27, 0x00 ; 0 45e: 88 85 ldd r24, Y+8 ; 0x08 460: 90 e0 ldi r25, 0x00 ; 0 462: 01 96 adiw r24, 0x01 ; 1 464: 8a 17 cp r24, r26 466: 9b 07 cpc r25, r27 468: 84 f7 brge .-32 ; 0x44a spi->tx_buffer[i] = echo->buffer[i]; } echo->tx_flag = 0; 46a: f9 01 movw r30, r18 46c: 13 86 std Z+11, r1 ; 0x0b spi->tx_flag = 1; 46e: 81 e0 ldi r24, 0x01 ; 1 470: 8a 83 std Y+2, r24 ; 0x02 } } 472: df 91 pop r29 474: cf 91 pop r28 476: 08 95 ret 00000478 : /* This function writes the heartbeat buffer when the heartbeat interrupt is fired */ void Make_RB(void){ //if (spi->first_message == 1){ if (RB->int_flag == 1){ 478: a0 91 04 20 lds r26, 0x2004 47c: b0 91 05 20 lds r27, 0x2005 480: 1c 96 adiw r26, 0x0c ; 12 482: 9c 91 ld r25, X 484: 1c 97 sbiw r26, 0x0c ; 12 486: 91 30 cpi r25, 0x01 ; 1 488: 79 f5 brne .+94 ; 0x4e8 PORTE.OUTTGL = PIN5_bm; 48a: 80 e2 ldi r24, 0x20 ; 32 48c: e0 e8 ldi r30, 0x80 ; 128 48e: f6 e0 ldi r31, 0x06 ; 6 490: 87 83 std Z+7, r24 ; 0x07 RB->tx_flag = 1; 492: 1b 96 adiw r26, 0x0b ; 11 494: 9c 93 st X, r25 496: 1b 97 sbiw r26, 0x0b ; 11 RB->buffer[0] = (uint8_t)(RB_HEARTBEAT>>8); 498: 87 e0 ldi r24, 0x07 ; 7 49a: 8c 93 st X, r24 RB->buffer[1] = fake_od->address; 49c: e0 91 00 20 lds r30, 0x2000 4a0: f0 91 01 20 lds r31, 0x2001 4a4: 82 81 ldd r24, Z+2 ; 0x02 4a6: 11 96 adiw r26, 0x01 ; 1 4a8: 8c 93 st X, r24 4aa: 11 97 sbiw r26, 0x01 ; 1 RB->buffer[2] = 0x67; 4ac: 87 e6 ldi r24, 0x67 ; 103 4ae: 12 96 adiw r26, 0x02 ; 2 4b0: 8c 93 st X, r24 4b2: 12 97 sbiw r26, 0x02 ; 2 RB->buffer[3] = 0x68; 4b4: 88 e6 ldi r24, 0x68 ; 104 4b6: 13 96 adiw r26, 0x03 ; 3 4b8: 8c 93 st X, r24 4ba: 13 97 sbiw r26, 0x03 ; 3 RB->buffer[4] = 0x69; 4bc: 89 e6 ldi r24, 0x69 ; 105 4be: 14 96 adiw r26, 0x04 ; 4 4c0: 8c 93 st X, r24 4c2: 14 97 sbiw r26, 0x04 ; 4 RB->buffer[5] = 0x70; 4c4: 80 e7 ldi r24, 0x70 ; 112 4c6: 15 96 adiw r26, 0x05 ; 5 4c8: 8c 93 st X, r24 4ca: 15 97 sbiw r26, 0x05 ; 5 RB->buffer[6] = 0x71; 4cc: 81 e7 ldi r24, 0x71 ; 113 4ce: 16 96 adiw r26, 0x06 ; 6 4d0: 8c 93 st X, r24 4d2: 16 97 sbiw r26, 0x06 ; 6 RB->buffer[7] = 0x72; 4d4: 82 e7 ldi r24, 0x72 ; 114 4d6: 17 96 adiw r26, 0x07 ; 7 4d8: 8c 93 st X, r24 4da: 17 97 sbiw r26, 0x07 ; 7 RB->len = 6; 4dc: 86 e0 ldi r24, 0x06 ; 6 4de: 1a 96 adiw r26, 0x0a ; 10 4e0: 8c 93 st X, r24 4e2: 1a 97 sbiw r26, 0x0a ; 10 RB->int_flag = 0; 4e4: 1c 96 adiw r26, 0x0c ; 12 4e6: 1c 92 st X, r1 4e8: 08 95 ret 000004ea : } //} } /* This function Echo's whatever is sent through spi */ void Echo(void){ 4ea: cf 93 push r28 4ec: df 93 push r29 if ((spi->rx_flag) == 1){ 4ee: 20 91 02 20 lds r18, 0x2002 4f2: 30 91 03 20 lds r19, 0x2003 4f6: f9 01 movw r30, r18 4f8: 81 81 ldd r24, Z+1 ; 0x01 4fa: 81 30 cpi r24, 0x01 ; 1 4fc: e9 f4 brne .+58 ; 0x538 //if ((spi->rx_buffer[0] == 0x00) && (spi->rx_buffer[1] = 0x00)){ for(uint8_t i=0;i<(spi->rx_len+2);i++){ echo->buffer[i] = spi->rx_buffer[i]; 4fe: c0 91 06 20 lds r28, 0x2006 502: d0 91 07 20 lds r29, 0x2007 506: 40 e0 ldi r20, 0x00 ; 0 508: 09 c0 rjmp .+18 ; 0x51c 50a: fe 01 movw r30, r28 50c: ea 0f add r30, r26 50e: fb 1f adc r31, r27 510: a2 0f add r26, r18 512: b3 1f adc r27, r19 514: 19 96 adiw r26, 0x09 ; 9 516: 8c 91 ld r24, X 518: 80 83 st Z, r24 /* This function Echo's whatever is sent through spi */ void Echo(void){ if ((spi->rx_flag) == 1){ //if ((spi->rx_buffer[0] == 0x00) && (spi->rx_buffer[1] = 0x00)){ for(uint8_t i=0;i<(spi->rx_len+2);i++){ 51a: 4f 5f subi r20, 0xFF ; 255 51c: f9 01 movw r30, r18 51e: 57 81 ldd r21, Z+7 ; 0x07 520: a4 2f mov r26, r20 522: b0 e0 ldi r27, 0x00 ; 0 524: 85 2f mov r24, r21 526: 90 e0 ldi r25, 0x00 ; 0 528: 01 96 adiw r24, 0x01 ; 1 52a: 8a 17 cp r24, r26 52c: 9b 07 cpc r25, r27 52e: 6c f7 brge .-38 ; 0x50a echo->buffer[i] = spi->rx_buffer[i]; } //fake_od->address = echo->buffer[1]; echo->len = spi->rx_len; 530: 5a 87 std Y+10, r21 ; 0x0a echo->tx_flag = 1; // Remember to ask to transmit buffer 532: 81 e0 ldi r24, 0x01 ; 1 534: 8b 87 std Y+11, r24 ; 0x0b spi->rx_flag = 0; 536: 11 82 std Z+1, r1 ; 0x01 //} } } 538: df 91 pop r29 53a: cf 91 pop r28 53c: 08 95 ret 0000053e <__vector_24>: /* This is an interrupt should have as little processing as possible in order to reduce interference */ ISR(SPIC_INT_vect){ 53e: 1f 92 push r1 540: 0f 92 push r0 542: 0f b6 in r0, 0x3f ; 63 544: 0f 92 push r0 546: 08 b6 in r0, 0x38 ; 56 548: 0f 92 push r0 54a: 0b b6 in r0, 0x3b ; 59 54c: 0f 92 push r0 54e: 11 24 eor r1, r1 550: 18 be out 0x38, r1 ; 56 552: 1b be out 0x3b, r1 ; 59 554: 8f 93 push r24 556: ef 93 push r30 558: ff 93 push r31 /* Set the interrupt flag to true so that the main loop will process the message. */ spi->int_flag = 1; 55a: e0 91 02 20 lds r30, 0x2002 55e: f0 91 03 20 lds r31, 0x2003 562: 81 e0 ldi r24, 0x01 ; 1 564: 80 83 st Z, r24 return; } 566: ff 91 pop r31 568: ef 91 pop r30 56a: 8f 91 pop r24 56c: 0f 90 pop r0 56e: 0b be out 0x3b, r0 ; 59 570: 0f 90 pop r0 572: 08 be out 0x38, r0 ; 56 574: 0f 90 pop r0 576: 0f be out 0x3f, r0 ; 63 578: 0f 90 pop r0 57a: 1f 90 pop r1 57c: 18 95 reti 0000057e <__vector_14>: /* Heartbeat interrupt */ ISR(TCC0_OVF_vect){ 57e: 1f 92 push r1 580: 0f 92 push r0 582: 0f b6 in r0, 0x3f ; 63 584: 0f 92 push r0 586: 08 b6 in r0, 0x38 ; 56 588: 0f 92 push r0 58a: 0b b6 in r0, 0x3b ; 59 58c: 0f 92 push r0 58e: 11 24 eor r1, r1 590: 18 be out 0x38, r1 ; 56 592: 1b be out 0x3b, r1 ; 59 594: 8f 93 push r24 596: ef 93 push r30 598: ff 93 push r31 /* Set the heartbeat timer flag so that the main loop will proces the message */ RB->int_flag = 1; 59a: e0 91 04 20 lds r30, 0x2004 59e: f0 91 05 20 lds r31, 0x2005 5a2: 81 e0 ldi r24, 0x01 ; 1 5a4: 84 87 std Z+12, r24 ; 0x0c return; } 5a6: ff 91 pop r31 5a8: ef 91 pop r30 5aa: 8f 91 pop r24 5ac: 0f 90 pop r0 5ae: 0b be out 0x3b, r0 ; 59 5b0: 0f 90 pop r0 5b2: 08 be out 0x38, r0 ; 56 5b4: 0f 90 pop r0 5b6: 0f be out 0x3f, r0 ; 63 5b8: 0f 90 pop r0 5ba: 1f 90 pop r1 5bc: 18 95 reti 000005be : CLKSYS_Main_ClockSource_Select(CLK_SCLKSEL_RC32M_gc); return; } /* --------------------------------------------------------------- */ void PWMTimer(void){ 5be: 0f 93 push r16 5c0: 1f 93 push r17 uint16_t compareValue = 0x0069; PORTF.DIR = 0xFF; // note: bitmask this foo! 5c2: 8f ef ldi r24, 0xFF ; 255 5c4: 80 93 a0 06 sts 0x06A0, r24 TC_SetPeriod (&TCF0, 0x00D2); //Set TC period 5c8: 00 e0 ldi r16, 0x00 ; 0 5ca: 1b e0 ldi r17, 0x0B ; 11 5cc: 82 ed ldi r24, 0xD2 ; 210 5ce: 90 e0 ldi r25, 0x00 ; 0 5d0: f8 01 movw r30, r16 5d2: 86 a3 std Z+38, r24 ; 0x26 5d4: 97 a3 std Z+39, r25 ; 0x27 TC0_ConfigWGM (&TCF0, TC_WGMODE_SS_gc); //Single slope mode 5d6: 80 e0 ldi r24, 0x00 ; 0 5d8: 9b e0 ldi r25, 0x0B ; 11 5da: 63 e0 ldi r22, 0x03 ; 3 5dc: 0e 94 a3 05 call 0xb46 ; 0xb46 TC0_EnableCCChannels( &TCF0, TC0_CCAEN_bm); //Enable compare channel A 5e0: 80 e0 ldi r24, 0x00 ; 0 5e2: 9b e0 ldi r25, 0x0B ; 11 5e4: 60 e1 ldi r22, 0x10 ; 16 5e6: 0e 94 bd 05 call 0xb7a ; 0xb7a TC0_ConfigClockSource( &TCF0, TC_CLKSEL_DIV1_gc); //Start timer by selecting clock source 5ea: 80 e0 ldi r24, 0x00 ; 0 5ec: 9b e0 ldi r25, 0x0B ; 11 5ee: 61 e0 ldi r22, 0x01 ; 1 5f0: 0e 94 97 05 call 0xb2e ; 0xb2e TC_SetCompareA (&TCF0, compareValue); //Setting our compare value 5f4: 89 e6 ldi r24, 0x69 ; 105 5f6: 90 e0 ldi r25, 0x00 ; 0 5f8: f8 01 movw r30, r16 5fa: 80 af std Z+56, r24 ; 0x38 5fc: 91 af std Z+57, r25 ; 0x39 return; } 5fe: 1f 91 pop r17 600: 0f 91 pop r16 602: 08 95 ret 00000604 : /* --------------------------------------------------------------- */ void CLK32Change(void){ /*Enable the internal 32MHz ring oscillator, wait till its stable and set as the main system clock*/ CLKSYS_Enable(OSC_RC32MEN_bm); 604: 80 91 50 00 lds r24, 0x0050 608: 82 60 ori r24, 0x02 ; 2 60a: 80 93 50 00 sts 0x0050, r24 60e: 03 c0 rjmp .+6 ; 0x616 while (CLKSYS_IsReady(OSC_RC32MRDY_bm) == 0) CLKSYS_Main_ClockSource_Select(CLK_SCLKSEL_RC32M_gc); 610: 81 e0 ldi r24, 0x01 ; 1 612: 0e 94 23 05 call 0xa46 ; 0xa46 void CLK32Change(void){ /*Enable the internal 32MHz ring oscillator, wait till its stable and set as the main system clock*/ CLKSYS_Enable(OSC_RC32MEN_bm); while (CLKSYS_IsReady(OSC_RC32MRDY_bm) == 0) 616: 80 91 51 00 lds r24, 0x0051 61a: 81 ff sbrs r24, 1 61c: f9 cf rjmp .-14 ; 0x610 CLKSYS_Main_ClockSource_Select(CLK_SCLKSEL_RC32M_gc); return; } 61e: 08 95 ret 00000620 : Make_RB(); } } void SPIinit(void){ 620: ef 92 push r14 622: 0f 93 push r16 //initialize SPI slave on port C SPI_SlaveInit (&spiSlaveC, //note: these might change for pic interface 624: 88 e0 ldi r24, 0x08 ; 8 626: 90 e2 ldi r25, 0x20 ; 32 628: 60 ec ldi r22, 0xC0 ; 192 62a: 78 e0 ldi r23, 0x08 ; 8 62c: 40 e4 ldi r20, 0x40 ; 64 62e: 56 e0 ldi r21, 0x06 ; 6 630: 20 e0 ldi r18, 0x00 ; 0 632: 04 e0 ldi r16, 0x04 ; 4 634: 32 e0 ldi r19, 0x02 ; 2 636: e3 2e mov r14, r19 638: 0e 94 d9 03 call 0x7b2 ; 0x7b2 false, SPI_MODE_1_gc, SPI_INTLVL_MED_gc); //Enable low and medium interrupts in teh interrupt controller PMIC.CTRL |= PMIC_MEDLVLEN_bm | PMIC_LOLVLEN_bm; 63c: e0 ea ldi r30, 0xA0 ; 160 63e: f0 e0 ldi r31, 0x00 ; 0 640: 82 81 ldd r24, Z+2 ; 0x02 642: 83 60 ori r24, 0x03 ; 3 644: 82 83 std Z+2, r24 ; 0x02 sei(); 646: 78 94 sei spi->first_message = 0; 648: e0 91 02 20 lds r30, 0x2002 64c: f0 91 03 20 lds r31, 0x2003 650: 15 8e std Z+29, r1 ; 0x1d return; } 652: 0f 91 pop r16 654: ef 90 pop r14 656: 08 95 ret 00000658
: void Process_SPI(void); void Process_Buffers(void); void Echo(void); void Make_RB(void); int main(void){ 658: 1f 93 push r17 65a: cf 93 push r28 65c: df 93 push r29 fake_od->address = RB_NODEID; 65e: e0 91 00 20 lds r30, 0x2000 662: f0 91 01 20 lds r31, 0x2001 666: 83 e2 ldi r24, 0x23 ; 35 668: 82 83 std Z+2, r24 ; 0x02 /* Set SS_PIC pin to output */ PORTD.DIR = 0b00000001; 66a: 91 e0 ldi r25, 0x01 ; 1 66c: 90 93 60 06 sts 0x0660, r25 /* Set Pins 1,4,5 for LED outputs */ PORTE.DIR = 0b00110010; 670: 82 e3 ldi r24, 0x32 ; 50 672: 80 93 80 06 sts 0x0680, r24 PORTD.OUT = PIN0_bm; 676: e0 e6 ldi r30, 0x60 ; 96 678: f6 e0 ldi r31, 0x06 ; 6 67a: 94 83 std Z+4, r25 ; 0x04 i = 0; 67c: 10 92 45 20 sts 0x2045, r1 680: 10 92 46 20 sts 0x2046, r1 spi->int_flag = 0; 684: e0 91 02 20 lds r30, 0x2002 688: f0 91 03 20 lds r31, 0x2003 68c: 10 82 st Z, r1 SPIinit(); 68e: 0e 94 10 03 call 0x620 ; 0x620 CLK32Change(); 692: 0e 94 02 03 call 0x604 ; 0x604 696: 80 e1 ldi r24, 0x10 ; 16 698: 97 e2 ldi r25, 0x27 ; 39 milliseconds can be achieved. */ void _delay_loop_2(uint16_t __count) { __asm__ volatile ( 69a: 20 e2 ldi r18, 0x20 ; 32 69c: 33 e0 ldi r19, 0x03 ; 3 69e: f9 01 movw r30, r18 6a0: 31 97 sbiw r30, 0x01 ; 1 6a2: f1 f7 brne .-4 ; 0x6a0 __ticks = (uint16_t) (__ms * 10.0); while(__ticks) { // wait 1/10 ms _delay_loop_2(((F_CPU) / 4e3) / 10); __ticks --; 6a4: 01 97 sbiw r24, 0x01 ; 1 __ticks = 1; else if (__tmp > 65535) { // __ticks = requested delay in 1/10 ms __ticks = (uint16_t) (__ms * 10.0); while(__ticks) 6a6: d9 f7 brne .-10 ; 0x69e /* Wait for new clock to stabalize */ _delay_ms(1000); PWMTimer(); 6a8: 0e 94 df 02 call 0x5be ; 0x5be Set up Timer/Counter 0 to work from CPICLK/64 with period of 31500 (a frequency of about 1 Hz) and enable overflow interrupt note: Initializing this timere will instantiate a heartbeat by nature of the interrupt linked to it */ TCC0.PER = 31650; 6ac: e0 e0 ldi r30, 0x00 ; 0 6ae: f8 e0 ldi r31, 0x08 ; 8 6b0: 82 ea ldi r24, 0xA2 ; 162 6b2: 9b e7 ldi r25, 0x7B ; 123 6b4: 86 a3 std Z+38, r24 ; 0x26 6b6: 97 a3 std Z+39, r25 ; 0x27 TCC0.CTRLA = (TCC0.CTRLA & ~TC0_CLKSEL_gm) | TC_CLKSEL_DIV1024_gc; 6b8: 80 91 00 08 lds r24, 0x0800 6bc: 80 7f andi r24, 0xF0 ; 240 6be: 87 60 ori r24, 0x07 ; 7 6c0: 80 93 00 08 sts 0x0800, r24 TCC0.INTCTRLA = (TCC0.INTCTRLA & ~TC0_OVFINTLVL_gm) | 6c4: 80 91 06 08 lds r24, 0x0806 6c8: 8c 7f andi r24, 0xFC ; 252 6ca: 82 60 ori r24, 0x02 ; 2 6cc: 86 83 std Z+6, r24 ; 0x06 TC_OVFINTLVL_MED_gc; PMIC.CTRL |= PMIC_MEDLVLEN_bm; 6ce: 80 91 a2 00 lds r24, 0x00A2 6d2: 82 60 ori r24, 0x02 ; 2 6d4: e0 ea ldi r30, 0xA0 ; 160 6d6: f0 e0 ldi r31, 0x00 ; 0 6d8: 82 83 std Z+2, r24 ; 0x02 6da: e0 91 02 20 lds r30, 0x2002 6de: f0 91 03 20 lds r31, 0x2003 6e2: 82 e0 ldi r24, 0x02 ; 2 spi->tx_buffer[6] = 0x04; spi->tx_buffer[7] = 0x05; spi->tx_buffer[8] = 0x06; spi->tx_buffer[9] = 0x35;*/ for(uint8_t i=2;itx_buffer[i] = 0x00; 6e4: 15 8a std Z+21, r1 ; 0x15 spi->tx_buffer[5] = 0x03; spi->tx_buffer[6] = 0x04; spi->tx_buffer[7] = 0x05; spi->tx_buffer[8] = 0x06; spi->tx_buffer[9] = 0x35;*/ for(uint8_t i=2;i spi->tx_buffer[i] = 0x00; } PORTE.OUT = PIN1_bm; 6ee: 82 e0 ldi r24, 0x02 ; 2 6f0: e0 e8 ldi r30, 0x80 ; 128 6f2: f6 e0 ldi r31, 0x06 ; 6 6f4: 84 83 std Z+4, r24 ; 0x04 for(uint8_t i=0;i<(spi->rx_len+2);i++){ echo->buffer[i] = spi->rx_buffer[i]; } //fake_od->address = echo->buffer[1]; echo->len = spi->rx_len; echo->tx_flag = 1; // Remember to ask to transmit buffer 6f6: 11 e0 ldi r17, 0x01 ; 1 spi->tx_buffer[i] = 0x00; } PORTE.OUT = PIN1_bm; for(;;){ Process_SPI(); 6f8: 0e 94 36 01 call 0x26c ; 0x26c Process_Buffers(); 6fc: 0e 94 f2 01 call 0x3e4 ; 0x3e4 //} } /* This function Echo's whatever is sent through spi */ void Echo(void){ if ((spi->rx_flag) == 1){ 700: 20 91 02 20 lds r18, 0x2002 704: 30 91 03 20 lds r19, 0x2003 708: f9 01 movw r30, r18 70a: 81 81 ldd r24, Z+1 ; 0x01 70c: 81 30 cpi r24, 0x01 ; 1 70e: e1 f4 brne .+56 ; 0x748 //if ((spi->rx_buffer[0] == 0x00) && (spi->rx_buffer[1] = 0x00)){ for(uint8_t i=0;i<(spi->rx_len+2);i++){ echo->buffer[i] = spi->rx_buffer[i]; 710: c0 91 06 20 lds r28, 0x2006 714: d0 91 07 20 lds r29, 0x2007 718: 40 e0 ldi r20, 0x00 ; 0 71a: 09 c0 rjmp .+18 ; 0x72e 71c: fe 01 movw r30, r28 71e: ea 0f add r30, r26 720: fb 1f adc r31, r27 722: a2 0f add r26, r18 724: b3 1f adc r27, r19 726: 19 96 adiw r26, 0x09 ; 9 728: 8c 91 ld r24, X 72a: 80 83 st Z, r24 /* This function Echo's whatever is sent through spi */ void Echo(void){ if ((spi->rx_flag) == 1){ //if ((spi->rx_buffer[0] == 0x00) && (spi->rx_buffer[1] = 0x00)){ for(uint8_t i=0;i<(spi->rx_len+2);i++){ 72c: 4f 5f subi r20, 0xFF ; 255 72e: f9 01 movw r30, r18 730: 57 81 ldd r21, Z+7 ; 0x07 732: a4 2f mov r26, r20 734: b0 e0 ldi r27, 0x00 ; 0 736: 85 2f mov r24, r21 738: 90 e0 ldi r25, 0x00 ; 0 73a: 01 96 adiw r24, 0x01 ; 1 73c: 8a 17 cp r24, r26 73e: 9b 07 cpc r25, r27 740: 6c f7 brge .-38 ; 0x71c echo->buffer[i] = spi->rx_buffer[i]; } //fake_od->address = echo->buffer[1]; echo->len = spi->rx_len; 742: 5a 87 std Y+10, r21 ; 0x0a echo->tx_flag = 1; // Remember to ask to transmit buffer 744: 1b 87 std Y+11, r17 ; 0x0b spi->rx_flag = 0; 746: 11 82 std Z+1, r1 ; 0x01 for(;;){ Process_SPI(); Process_Buffers(); Echo(); Make_RB(); 748: 0e 94 3c 02 call 0x478 ; 0x478 74c: d5 cf rjmp .-86 ; 0x6f8 0000074e : bool lsbFirst, SPI_MODE_t mode, SPI_INTLVL_t intLevel, bool clk2x, SPI_PRESCALER_t clockDivision) { 74e: af 92 push r10 750: cf 92 push r12 752: ef 92 push r14 754: 0f 93 push r16 756: dc 01 movw r26, r24 758: fb 01 movw r30, r22 spi->module = module; 75a: 6d 93 st X+, r22 75c: 7c 93 st X, r23 75e: 11 97 sbiw r26, 0x01 ; 1 spi->port = port; 760: 12 96 adiw r26, 0x02 ; 2 762: 4d 93 st X+, r20 764: 5c 93 st X, r21 766: 13 97 sbiw r26, 0x03 ; 3 spi->interrupted = false; 768: 14 96 adiw r26, 0x04 ; 4 76a: 1c 92 st X, r1 76c: 14 97 sbiw r26, 0x04 ; 4 spi->module->CTRL = clockDivision | /* SPI prescaler. */ 76e: cc 20 and r12, r12 770: 11 f4 brne .+4 ; 0x776 772: 90 e0 ldi r25, 0x00 ; 0 774: 01 c0 rjmp .+2 ; 0x778 776: 90 e8 ldi r25, 0x80 ; 128 778: 22 23 and r18, r18 77a: 11 f4 brne .+4 ; 0x780 77c: 80 e0 ldi r24, 0x00 ; 0 77e: 01 c0 rjmp .+2 ; 0x782 780: 80 e2 ldi r24, 0x20 ; 32 782: 00 65 ori r16, 0x50 ; 80 784: 0a 29 or r16, r10 786: 90 2b or r25, r16 788: 89 2b or r24, r25 78a: 80 83 st Z, r24 (lsbFirst ? SPI_DORD_bm : 0) | /* Data order. */ SPI_MASTER_bm | /* SPI master. */ mode; /* SPI mode. */ /* Interrupt level. */ spi->module->INTCTRL = intLevel; 78c: ed 91 ld r30, X+ 78e: fc 91 ld r31, X 790: 11 97 sbiw r26, 0x01 ; 1 792: e1 82 std Z+1, r14 ; 0x01 /* No assigned data packet. */ spi->dataPacket = NULL; 794: 15 96 adiw r26, 0x05 ; 5 796: 1d 92 st X+, r1 798: 1c 92 st X, r1 79a: 16 97 sbiw r26, 0x06 ; 6 /* MOSI and SCK as output. */ spi->port->DIRSET = SPI_MOSI_bm | SPI_SCK_bm; 79c: 12 96 adiw r26, 0x02 ; 2 79e: ed 91 ld r30, X+ 7a0: fc 91 ld r31, X 7a2: 13 97 sbiw r26, 0x03 ; 3 7a4: 80 ea ldi r24, 0xA0 ; 160 7a6: 81 83 std Z+1, r24 ; 0x01 } 7a8: 0f 91 pop r16 7aa: ef 90 pop r14 7ac: cf 90 pop r12 7ae: af 90 pop r10 7b0: 08 95 ret 000007b2 : SPI_t *module, PORT_t *port, bool lsbFirst, SPI_MODE_t mode, SPI_INTLVL_t intLevel) { 7b2: ef 92 push r14 7b4: 0f 93 push r16 7b6: dc 01 movw r26, r24 7b8: fb 01 movw r30, r22 /* SPI module. */ spi->module = module; 7ba: 6d 93 st X+, r22 7bc: 7c 93 st X, r23 7be: 11 97 sbiw r26, 0x01 ; 1 spi->port = port; 7c0: 12 96 adiw r26, 0x02 ; 2 7c2: 4d 93 st X+, r20 7c4: 5c 93 st X, r21 7c6: 13 97 sbiw r26, 0x03 ; 3 spi->module->CTRL = SPI_ENABLE_bm | /* Enable SPI module. */ 7c8: 22 23 and r18, r18 7ca: 11 f4 brne .+4 ; 0x7d0 7cc: 80 e4 ldi r24, 0x40 ; 64 7ce: 01 c0 rjmp .+2 ; 0x7d2 7d0: 80 e6 ldi r24, 0x60 ; 96 7d2: 80 2b or r24, r16 7d4: 80 83 st Z, r24 (lsbFirst ? SPI_DORD_bm : 0) | /* Data order. */ mode; /* SPI mode. */ /* Interrupt level. */ spi->module->INTCTRL = intLevel; 7d6: ed 91 ld r30, X+ 7d8: fc 91 ld r31, X 7da: 11 97 sbiw r26, 0x01 ; 1 7dc: e1 82 std Z+1, r14 ; 0x01 /* MISO as output. */ spi->port->DIRSET = SPI_MISO_bm; 7de: 12 96 adiw r26, 0x02 ; 2 7e0: ed 91 ld r30, X+ 7e2: fc 91 ld r31, X 7e4: 13 97 sbiw r26, 0x03 ; 3 7e6: 80 e4 ldi r24, 0x40 ; 64 7e8: 81 83 std Z+1, r24 ; 0x01 } 7ea: 0f 91 pop r16 7ec: ef 90 pop r14 7ee: 08 95 ret 000007f0 : const uint8_t *transmitData, uint8_t *receiveData, uint8_t bytesToTransceive, PORT_t *ssPort, uint8_t ssPinMask) { 7f0: ef 92 push r14 7f2: 0f 93 push r16 7f4: 1f 93 push r17 7f6: fc 01 movw r30, r24 dataPacket->ssPort = ssPort; 7f8: 00 83 st Z, r16 7fa: 11 83 std Z+1, r17 ; 0x01 dataPacket->ssPinMask = ssPinMask; 7fc: e2 82 std Z+2, r14 ; 0x02 dataPacket->transmitData = transmitData; 7fe: 63 83 std Z+3, r22 ; 0x03 800: 74 83 std Z+4, r23 ; 0x04 dataPacket->receiveData = receiveData; 802: 45 83 std Z+5, r20 ; 0x05 804: 56 83 std Z+6, r21 ; 0x06 dataPacket->bytesToTransceive = bytesToTransceive; 806: 27 83 std Z+7, r18 ; 0x07 dataPacket->bytesTransceived = 0; 808: 10 86 std Z+8, r1 ; 0x08 dataPacket->complete = false; 80a: 11 86 std Z+9, r1 ; 0x09 } 80c: 1f 91 pop r17 80e: 0f 91 pop r16 810: ef 90 pop r14 812: 08 95 ret 00000814 : * a pointer to the related SPI_Master_t struct as argument. * * \param spi Pointer to the modules own SPI_Master_t struct. */ void SPI_MasterInterruptHandler(SPI_Master_t *spi) { 814: cf 93 push r28 816: df 93 push r29 818: dc 01 movw r26, r24 uint8_t data; uint8_t bytesTransceived = spi->dataPacket->bytesTransceived; 81a: 15 96 adiw r26, 0x05 ; 5 81c: cd 91 ld r28, X+ 81e: dc 91 ld r29, X 820: 16 97 sbiw r26, 0x06 ; 6 822: 98 85 ldd r25, Y+8 ; 0x08 /* If SS pin interrupt (SS used and pulled low). * No data received at this point. */ if ( !(spi->module->CTRL & SPI_MASTER_bm) ) { 824: ed 91 ld r30, X+ 826: fc 91 ld r31, X 828: 11 97 sbiw r26, 0x01 ; 1 82a: 80 81 ld r24, Z 82c: 84 fd sbrc r24, 4 82e: 05 c0 rjmp .+10 ; 0x83a spi->interrupted = true; 830: 81 e0 ldi r24, 0x01 ; 1 832: 14 96 adiw r26, 0x04 ; 4 834: 8c 93 st X, r24 836: 14 97 sbiw r26, 0x04 ; 4 838: 24 c0 rjmp .+72 ; 0x882 } else { /* Data interrupt. */ /* Store received data. */ data = spi->module->DATA; 83a: 83 81 ldd r24, Z+3 ; 0x03 spi->dataPacket->receiveData[bytesTransceived] = data; 83c: ed 81 ldd r30, Y+5 ; 0x05 83e: fe 81 ldd r31, Y+6 ; 0x06 840: e9 0f add r30, r25 842: f1 1d adc r31, r1 844: 80 83 st Z, r24 /* Next byte. */ bytesTransceived++; 846: 9f 5f subi r25, 0xFF ; 255 /* If more data. */ if (bytesTransceived < spi->dataPacket->bytesToTransceive) { 848: 15 96 adiw r26, 0x05 ; 5 84a: ed 91 ld r30, X+ 84c: fc 91 ld r31, X 84e: 16 97 sbiw r26, 0x06 ; 6 850: 87 81 ldd r24, Z+7 ; 0x07 852: 98 17 cp r25, r24 854: 58 f4 brcc .+22 ; 0x86c /* Put data byte in transmit data register. */ data = spi->dataPacket->transmitData[bytesTransceived]; 856: 03 80 ldd r0, Z+3 ; 0x03 858: f4 81 ldd r31, Z+4 ; 0x04 85a: e0 2d mov r30, r0 85c: e9 0f add r30, r25 85e: f1 1d adc r31, r1 860: 80 81 ld r24, Z spi->module->DATA = data; 862: ed 91 ld r30, X+ 864: fc 91 ld r31, X 866: 11 97 sbiw r26, 0x01 ; 1 868: 83 83 std Z+3, r24 ; 0x03 86a: 0b c0 rjmp .+22 ; 0x882 /* Transmission complete. */ else { /* Release SS to slave(s). */ uint8_t ssPinMask = spi->dataPacket->ssPinMask; 86c: 82 81 ldd r24, Z+2 ; 0x02 SPI_MasterSSHigh(spi->dataPacket->ssPort, ssPinMask); 86e: 01 90 ld r0, Z+ 870: f0 81 ld r31, Z 872: e0 2d mov r30, r0 874: 85 83 std Z+5, r24 ; 0x05 spi->dataPacket->complete = true; 876: 15 96 adiw r26, 0x05 ; 5 878: ed 91 ld r30, X+ 87a: fc 91 ld r31, X 87c: 16 97 sbiw r26, 0x06 ; 6 87e: 81 e0 ldi r24, 0x01 ; 1 880: 81 87 std Z+9, r24 ; 0x09 } } /* Write back bytesTransceived to data packet. */ spi->dataPacket->bytesTransceived = bytesTransceived; 882: 15 96 adiw r26, 0x05 ; 5 884: ed 91 ld r30, X+ 886: fc 91 ld r31, X 888: 16 97 sbiw r26, 0x06 ; 6 88a: 90 87 std Z+8, r25 ; 0x08 } 88c: df 91 pop r29 88e: cf 91 pop r28 890: 08 95 ret 00000892 : * \retval SPI_BUSY The SPI module is busy. * \retval SPI_INTERRUPTED The transmission was interrupted by another master. */ uint8_t SPI_MasterInterruptTransceivePacket(SPI_Master_t *spi, SPI_DataPacket_t *dataPacket) { 892: cf 93 push r28 894: df 93 push r29 896: dc 01 movw r26, r24 898: eb 01 movw r28, r22 uint8_t data; bool interrupted = spi->interrupted; 89a: 14 96 adiw r26, 0x04 ; 4 89c: 9c 91 ld r25, X 89e: 14 97 sbiw r26, 0x04 ; 4 /* If no packets sent so far. */ if (spi->dataPacket == NULL) { 8a0: 15 96 adiw r26, 0x05 ; 5 8a2: ed 91 ld r30, X+ 8a4: fc 91 ld r31, X 8a6: 16 97 sbiw r26, 0x06 ; 6 8a8: 30 97 sbiw r30, 0x00 ; 0 8aa: 29 f4 brne .+10 ; 0x8b6 spi->dataPacket = dataPacket; 8ac: 15 96 adiw r26, 0x05 ; 5 8ae: 6d 93 st X+, r22 8b0: 7c 93 st X, r23 8b2: 16 97 sbiw r26, 0x06 ; 6 8b4: 10 c0 rjmp .+32 ; 0x8d6 } /* If ongoing transmission. */ else if (spi->dataPacket->complete == false) { 8b6: 81 85 ldd r24, Z+9 ; 0x09 8b8: 88 23 and r24, r24 8ba: 11 f4 brne .+4 ; 0x8c0 8bc: 82 e0 ldi r24, 0x02 ; 2 8be: 28 c0 rjmp .+80 ; 0x910 return (SPI_BUSY); } /* If interrupted by other master. */ else if (interrupted) { 8c0: 99 23 and r25, r25 8c2: 49 f0 breq .+18 ; 0x8d6 /* If SS released. */ if (spi->port->OUT & SPI_SS_bm) { 8c4: 12 96 adiw r26, 0x02 ; 2 8c6: ed 91 ld r30, X+ 8c8: fc 91 ld r31, X 8ca: 13 97 sbiw r26, 0x03 ; 3 8cc: 84 81 ldd r24, Z+4 ; 0x04 8ce: 84 fd sbrc r24, 4 8d0: 02 c0 rjmp .+4 ; 0x8d6 8d2: 81 e0 ldi r24, 0x01 ; 1 8d4: 1d c0 rjmp .+58 ; 0x910 } } /* NOT interrupted by other master. * Start transmission. */ spi->dataPacket = dataPacket; 8d6: 15 96 adiw r26, 0x05 ; 5 8d8: cd 93 st X+, r28 8da: dc 93 st X, r29 8dc: 16 97 sbiw r26, 0x06 ; 6 spi->dataPacket->complete = false; 8de: 19 86 std Y+9, r1 ; 0x09 spi->interrupted = false; 8e0: 14 96 adiw r26, 0x04 ; 4 8e2: 1c 92 st X, r1 8e4: 14 97 sbiw r26, 0x04 ; 4 /* SS to slave(s) low.*/ uint8_t ssPinMask = spi->dataPacket->ssPinMask; 8e6: 8a 81 ldd r24, Y+2 ; 0x02 SPI_MasterSSLow(spi->dataPacket->ssPort, ssPinMask); 8e8: e8 81 ld r30, Y 8ea: f9 81 ldd r31, Y+1 ; 0x01 8ec: 86 83 std Z+6, r24 ; 0x06 spi->dataPacket->bytesTransceived = 0; 8ee: 15 96 adiw r26, 0x05 ; 5 8f0: ed 91 ld r30, X+ 8f2: fc 91 ld r31, X 8f4: 16 97 sbiw r26, 0x06 ; 6 8f6: 10 86 std Z+8, r1 ; 0x08 /* Start sending data. */ data = spi->dataPacket->transmitData[0]; 8f8: 15 96 adiw r26, 0x05 ; 5 8fa: ed 91 ld r30, X+ 8fc: fc 91 ld r31, X 8fe: 16 97 sbiw r26, 0x06 ; 6 900: 03 80 ldd r0, Z+3 ; 0x03 902: f4 81 ldd r31, Z+4 ; 0x04 904: e0 2d mov r30, r0 906: 80 81 ld r24, Z spi->module->DATA = data; 908: ed 91 ld r30, X+ 90a: fc 91 ld r31, X 90c: 83 83 std Z+3, r24 ; 0x03 90e: 80 e0 ldi r24, 0x00 ; 0 /* Successs */ return (SPI_OK); } 910: df 91 pop r29 912: cf 91 pop r28 914: 08 95 ret 00000916 : * \param TXdata Data to transmit to slave. * * \return Data received from slave. */ uint8_t SPI_MasterTransceiveByte(SPI_Master_t *spi, uint8_t TXdata) { 916: fc 01 movw r30, r24 /* Send pattern. */ spi->module->DATA = TXdata; 918: a0 81 ld r26, Z 91a: b1 81 ldd r27, Z+1 ; 0x01 91c: 13 96 adiw r26, 0x03 ; 3 91e: 6c 93 st X, r22 /* Wait for transmission complete. */ while(!(spi->module->STATUS & SPI_IF_bm)) { 920: 01 90 ld r0, Z+ 922: f0 81 ld r31, Z 924: e0 2d mov r30, r0 926: 82 81 ldd r24, Z+2 ; 0x02 928: 87 ff sbrs r24, 7 92a: fd cf rjmp .-6 ; 0x926 } /* Read received data. */ uint8_t result = spi->module->DATA; 92c: 83 81 ldd r24, Z+3 ; 0x03 return(result); } 92e: 08 95 ret 00000930 : * \retval true Success * \retval false Failure */ bool SPI_MasterTransceivePacket(SPI_Master_t *spi, SPI_DataPacket_t *dataPacket) { 930: cf 93 push r28 932: df 93 push r29 934: ec 01 movw r28, r24 936: fb 01 movw r30, r22 /* Check if data packet has been created. */ if(dataPacket == NULL) { 938: 61 15 cp r22, r1 93a: 71 05 cpc r23, r1 93c: 11 f4 brne .+4 ; 0x942 93e: 80 e0 ldi r24, 0x00 ; 0 940: 37 c0 rjmp .+110 ; 0x9b0 return false; } /* Assign datapacket to SPI module. */ spi->dataPacket = dataPacket; 942: 6d 83 std Y+5, r22 ; 0x05 944: 7e 83 std Y+6, r23 ; 0x06 uint8_t ssPinMask = spi->dataPacket->ssPinMask; 946: 42 81 ldd r20, Z+2 ; 0x02 /* If SS signal to slave(s). */ if (spi->dataPacket->ssPort != NULL) { 948: a0 81 ld r26, Z 94a: b1 81 ldd r27, Z+1 ; 0x01 94c: 10 97 sbiw r26, 0x00 ; 0 94e: 11 f0 breq .+4 ; 0x954 /* SS to slave(s) low. */ SPI_MasterSSLow(spi->dataPacket->ssPort, ssPinMask); 950: 16 96 adiw r26, 0x06 ; 6 952: 4c 93 st X, r20 } /* Transceive bytes. */ uint8_t bytesTransceived = 0; uint8_t bytesToTransceive = dataPacket->bytesToTransceive; 954: 67 81 ldd r22, Z+7 ; 0x07 956: 90 e0 ldi r25, 0x00 ; 0 958: 1a c0 rjmp .+52 ; 0x98e while (bytesTransceived < bytesToTransceive) { /* Send pattern. */ uint8_t data = spi->dataPacket->transmitData[bytesTransceived]; 95a: 29 2f mov r18, r25 95c: 30 e0 ldi r19, 0x00 ; 0 95e: 03 80 ldd r0, Z+3 ; 0x03 960: f4 81 ldd r31, Z+4 ; 0x04 962: e0 2d mov r30, r0 964: e2 0f add r30, r18 966: f3 1f adc r31, r19 968: 80 81 ld r24, Z spi->module->DATA = data; 96a: e8 81 ld r30, Y 96c: f9 81 ldd r31, Y+1 ; 0x01 96e: 83 83 std Z+3, r24 ; 0x03 /* Wait for transmission complete. */ while(!(spi->module->STATUS & SPI_IF_bm)) { 970: e8 81 ld r30, Y 972: f9 81 ldd r31, Y+1 ; 0x01 974: 82 81 ldd r24, Z+2 ; 0x02 976: 87 ff sbrs r24, 7 978: fd cf rjmp .-6 ; 0x974 } /* Read received data. */ data = spi->module->DATA; 97a: 83 81 ldd r24, Z+3 ; 0x03 spi->dataPacket->receiveData[bytesTransceived] = data; 97c: ed 81 ldd r30, Y+5 ; 0x05 97e: fe 81 ldd r31, Y+6 ; 0x06 980: 05 80 ldd r0, Z+5 ; 0x05 982: f6 81 ldd r31, Z+6 ; 0x06 984: e0 2d mov r30, r0 986: e2 0f add r30, r18 988: f3 1f adc r31, r19 98a: 80 83 st Z, r24 bytesTransceived++; 98c: 9f 5f subi r25, 0xFF ; 255 98e: ed 81 ldd r30, Y+5 ; 0x05 990: fe 81 ldd r31, Y+6 ; 0x06 } /* Transceive bytes. */ uint8_t bytesTransceived = 0; uint8_t bytesToTransceive = dataPacket->bytesToTransceive; while (bytesTransceived < bytesToTransceive) { 992: 96 17 cp r25, r22 994: 10 f3 brcs .-60 ; 0x95a bytesTransceived++; } /* If SS signal to slave(s). */ if (spi->dataPacket->ssPort != NULL) { 996: 01 90 ld r0, Z+ 998: f0 81 ld r31, Z 99a: e0 2d mov r30, r0 99c: 30 97 sbiw r30, 0x00 ; 0 99e: 09 f0 breq .+2 ; 0x9a2 /* Release SS to slave(s). */ SPI_MasterSSHigh(spi->dataPacket->ssPort, ssPinMask); 9a0: 45 83 std Z+5, r20 ; 0x05 } /* Set variables to indicate that transmission is complete. */ spi->dataPacket->bytesTransceived = bytesTransceived; 9a2: ed 81 ldd r30, Y+5 ; 0x05 9a4: fe 81 ldd r31, Y+6 ; 0x06 9a6: 60 87 std Z+8, r22 ; 0x08 spi->dataPacket->complete = true; 9a8: ed 81 ldd r30, Y+5 ; 0x05 9aa: fe 81 ldd r31, Y+6 ; 0x06 9ac: 81 e0 ldi r24, 0x01 ; 1 9ae: 81 87 std Z+9, r24 ; 0x09 /* Report success. */ return true; } 9b0: df 91 pop r29 9b2: cf 91 pop r28 9b4: 08 95 ret 000009b6 : * * \param address A pointer to the address to write to. * \param value The value to put in to the register. */ void CCPWrite( volatile uint8_t * address, uint8_t value ) { 9b6: 0f 93 push r16 9b8: df 93 push r29 9ba: cf 93 push r28 9bc: 0f 92 push r0 9be: cd b7 in r28, 0x3d ; 61 9c0: de b7 in r29, 0x3e ; 62 // Restore global interrupt setting from scratch register. asm("out 0x3F, R1"); #elif defined __GNUC__ AVR_ENTER_CRITICAL_REGION( ); 9c2: 2f b7 in r18, 0x3f ; 63 9c4: 29 83 std Y+1, r18 ; 0x01 9c6: f8 94 cli volatile uint8_t * tmpAddr = address; #ifdef RAMPZ RAMPZ = 0; 9c8: 1b be out 0x3b, r1 ; 59 #endif asm volatile( 9ca: fc 01 movw r30, r24 9cc: 08 ed ldi r16, 0xD8 ; 216 9ce: 04 bf out 0x34, r16 ; 52 9d0: 60 83 st Z, r22 : : "r" (tmpAddr), "r" (value), "M" (CCP_IOREG_gc), "i" (&CCP) : "r16", "r30", "r31" ); AVR_LEAVE_CRITICAL_REGION( ); 9d2: 89 81 ldd r24, Y+1 ; 0x01 9d4: 8f bf out 0x3f, r24 ; 63 #endif } 9d6: 0f 90 pop r0 9d8: cf 91 pop r28 9da: df 91 pop r29 9dc: 0f 91 pop r16 9de: 08 95 ret 000009e0 : */ void CLKSYS_XOSC_Config( OSC_FRQRANGE_t freqRange, bool lowPower32kHz, OSC_XOSCSEL_t xoscModeSelection ) { OSC.XOSCCTRL = (uint8_t) freqRange | 9e0: 66 23 and r22, r22 9e2: 11 f4 brne .+4 ; 0x9e8 9e4: 90 e0 ldi r25, 0x00 ; 0 9e6: 01 c0 rjmp .+2 ; 0x9ea 9e8: 90 e2 ldi r25, 0x20 ; 32 9ea: 48 2b or r20, r24 9ec: 94 2b or r25, r20 9ee: e0 e5 ldi r30, 0x50 ; 80 9f0: f0 e0 ldi r31, 0x00 ; 0 9f2: 92 83 std Z+2, r25 ; 0x02 ( lowPower32kHz ? OSC_X32KLPM_bm : 0 ) | xoscModeSelection; } 9f4: 08 95 ret 000009f6 : * from 1 to 31, inclusive. */ void CLKSYS_PLL_Config( OSC_PLLSRC_t clockSource, uint8_t factor ) { factor &= OSC_PLLFAC_gm; OSC.PLLCTRL = (uint8_t) clockSource | ( factor << OSC_PLLFAC_gp ); 9f6: 6f 71 andi r22, 0x1F ; 31 9f8: 68 2b or r22, r24 9fa: e0 e5 ldi r30, 0x50 ; 80 9fc: f0 e0 ldi r31, 0x00 ; 0 9fe: 65 83 std Z+5, r22 ; 0x05 } a00: 08 95 ret 00000a02 : * * \return Non-zero if oscillator was disabled successfully. */ uint8_t CLKSYS_Disable( uint8_t oscSel ) { OSC.CTRL &= ~oscSel; a02: e0 e5 ldi r30, 0x50 ; 80 a04: f0 e0 ldi r31, 0x00 ; 0 a06: 20 81 ld r18, Z a08: 98 2f mov r25, r24 a0a: 90 95 com r25 a0c: 92 23 and r25, r18 a0e: 90 83 st Z, r25 uint8_t clkEnabled = OSC.CTRL & oscSel; a10: 90 81 ld r25, Z return clkEnabled; } a12: 89 23 and r24, r25 a14: 08 95 ret 00000a16 : * \param PSBCfactor Prescaler B and C division factor, in the combination * of (1,1), (1,2), (4,1) or (2,2). */ void CLKSYS_Prescalers_Config( CLK_PSADIV_t PSAfactor, CLK_PSBCDIV_t PSBCfactor ) { a16: 0f 93 push r16 a18: df 93 push r29 a1a: cf 93 push r28 a1c: 0f 92 push r0 a1e: cd b7 in r28, 0x3d ; 61 a20: de b7 in r29, 0x3e ; 62 // Restore global interrupt setting from scratch register. asm("out 0x3F, R1"); #elif defined __GNUC__ AVR_ENTER_CRITICAL_REGION( ); a22: 9f b7 in r25, 0x3f ; 63 a24: 99 83 std Y+1, r25 ; 0x01 a26: f8 94 cli volatile uint8_t * tmpAddr = address; #ifdef RAMPZ RAMPZ = 0; a28: 1b be out 0x3b, r1 ; 59 #endif asm volatile( a2a: 68 2b or r22, r24 a2c: 81 e4 ldi r24, 0x41 ; 65 a2e: 90 e0 ldi r25, 0x00 ; 0 a30: fc 01 movw r30, r24 a32: 08 ed ldi r16, 0xD8 ; 216 a34: 04 bf out 0x34, r16 ; 52 a36: 60 83 st Z, r22 : : "r" (tmpAddr), "r" (value), "M" (CCP_IOREG_gc), "i" (&CCP) : "r16", "r30", "r31" ); AVR_LEAVE_CRITICAL_REGION( ); a38: 89 81 ldd r24, Y+1 ; 0x01 a3a: 8f bf out 0x3f, r24 ; 63 void CLKSYS_Prescalers_Config( CLK_PSADIV_t PSAfactor, CLK_PSBCDIV_t PSBCfactor ) { uint8_t PSconfig = (uint8_t) PSAfactor | PSBCfactor; CCPWrite( &CLK.PSCTRL, PSconfig ); } a3c: 0f 90 pop r0 a3e: cf 91 pop r28 a40: df 91 pop r29 a42: 0f 91 pop r16 a44: 08 95 ret 00000a46 : * prescaler block. * * \return Non-zero if change was successful. */ uint8_t CLKSYS_Main_ClockSource_Select( CLK_SCLKSEL_t clockSource ) { a46: 0f 93 push r16 a48: df 93 push r29 a4a: cf 93 push r28 a4c: 0f 92 push r0 a4e: cd b7 in r28, 0x3d ; 61 a50: de b7 in r29, 0x3e ; 62 uint8_t clkCtrl = ( CLK.CTRL & ~CLK_SCLKSEL_gm ) | clockSource; a52: 20 91 40 00 lds r18, 0x0040 // Restore global interrupt setting from scratch register. asm("out 0x3F, R1"); #elif defined __GNUC__ AVR_ENTER_CRITICAL_REGION( ); a56: 9f b7 in r25, 0x3f ; 63 a58: 99 83 std Y+1, r25 ; 0x01 a5a: f8 94 cli volatile uint8_t * tmpAddr = address; #ifdef RAMPZ RAMPZ = 0; a5c: 1b be out 0x3b, r1 ; 59 #endif asm volatile( a5e: a0 e4 ldi r26, 0x40 ; 64 a60: b0 e0 ldi r27, 0x00 ; 0 a62: 28 7f andi r18, 0xF8 ; 248 a64: 28 2b or r18, r24 a66: fd 01 movw r30, r26 a68: 08 ed ldi r16, 0xD8 ; 216 a6a: 04 bf out 0x34, r16 ; 52 a6c: 20 83 st Z, r18 : : "r" (tmpAddr), "r" (value), "M" (CCP_IOREG_gc), "i" (&CCP) : "r16", "r30", "r31" ); AVR_LEAVE_CRITICAL_REGION( ); a6e: 99 81 ldd r25, Y+1 ; 0x01 a70: 9f bf out 0x3f, r25 ; 63 */ uint8_t CLKSYS_Main_ClockSource_Select( CLK_SCLKSEL_t clockSource ) { uint8_t clkCtrl = ( CLK.CTRL & ~CLK_SCLKSEL_gm ) | clockSource; CCPWrite( &CLK.CTRL, clkCtrl ); clkCtrl = ( CLK.CTRL & clockSource ); a72: 9c 91 ld r25, X return clkCtrl; } a74: 89 23 and r24, r25 a76: 0f 90 pop r0 a78: cf 91 pop r28 a7a: df 91 pop r29 a7c: 0f 91 pop r16 a7e: 08 95 ret 00000a80 : * * \param clockSource Clock source to use for the RTC. */ void CLKSYS_RTC_ClockSource_Enable( CLK_RTCSRC_t clockSource ) { CLK.RTCCTRL = ( CLK.RTCCTRL & ~CLK_RTCSRC_gm ) | a80: e0 e4 ldi r30, 0x40 ; 64 a82: f0 e0 ldi r31, 0x00 ; 0 a84: 93 81 ldd r25, Z+3 ; 0x03 a86: 91 7f andi r25, 0xF1 ; 241 a88: 91 60 ori r25, 0x01 ; 1 a8a: 98 2b or r25, r24 a8c: 93 83 std Z+3, r25 ; 0x03 clockSource | CLK_RTCEN_bm; } a8e: 08 95 ret 00000a90 : * \param clkSource Clock source to calibrate, either OSC_RC2MCREF_bm or * OSC_RC32MCREF_bm. * \param extReference True if external crystal should be used as reference. */ void CLKSYS_AutoCalibration_Enable( uint8_t clkSource, bool extReference ) { a90: 28 2f mov r18, r24 OSC.DFLLCTRL = ( OSC.DFLLCTRL & ~clkSource ) | a92: 30 91 56 00 lds r19, 0x0056 a96: 66 23 and r22, r22 a98: 11 f0 breq .+4 ; 0xa9e a9a: 98 2f mov r25, r24 a9c: 01 c0 rjmp .+2 ; 0xaa0 a9e: 90 e0 ldi r25, 0x00 ; 0 aa0: 82 2f mov r24, r18 aa2: 80 95 com r24 aa4: 83 23 and r24, r19 aa6: 98 2b or r25, r24 aa8: e0 e5 ldi r30, 0x50 ; 80 aaa: f0 e0 ldi r31, 0x00 ; 0 aac: 96 83 std Z+6, r25 ; 0x06 ( extReference ? clkSource : 0 ); if (clkSource == OSC_RC2MCREF_bm) { aae: 21 30 cpi r18, 0x01 ; 1 ab0: 31 f4 brne .+12 ; 0xabe DFLLRC2M.CTRL |= DFLL_ENABLE_bm; ab2: 80 91 68 00 lds r24, 0x0068 ab6: 81 60 ori r24, 0x01 ; 1 ab8: 80 93 68 00 sts 0x0068, r24 abc: 08 95 ret } else if (clkSource == OSC_RC32MCREF_bm) { abe: 22 30 cpi r18, 0x02 ; 2 ac0: 29 f4 brne .+10 ; 0xacc DFLLRC32M.CTRL |= DFLL_ENABLE_bm; ac2: 80 91 60 00 lds r24, 0x0060 ac6: 81 60 ori r24, 0x01 ; 1 ac8: 80 93 60 00 sts 0x0060, r24 acc: 08 95 ret 00000ace : * XOSCFD _will_ issue the XOSCF Non-maskable Interrupt (NMI) regardless of * any interrupt priorities and settings. Therefore, make sure that a handler * is implemented for the XOSCF NMI when you enable it. */ void CLKSYS_XOSC_FailureDetection_Enable( void ) { ace: 0f 93 push r16 ad0: df 93 push r29 ad2: cf 93 push r28 ad4: 0f 92 push r0 ad6: cd b7 in r28, 0x3d ; 61 ad8: de b7 in r29, 0x3e ; 62 // Restore global interrupt setting from scratch register. asm("out 0x3F, R1"); #elif defined __GNUC__ AVR_ENTER_CRITICAL_REGION( ); ada: 8f b7 in r24, 0x3f ; 63 adc: 89 83 std Y+1, r24 ; 0x01 ade: f8 94 cli volatile uint8_t * tmpAddr = address; #ifdef RAMPZ RAMPZ = 0; ae0: 1b be out 0x3b, r1 ; 59 #endif asm volatile( ae2: 23 e0 ldi r18, 0x03 ; 3 ae4: 83 e5 ldi r24, 0x53 ; 83 ae6: 90 e0 ldi r25, 0x00 ; 0 ae8: fc 01 movw r30, r24 aea: 08 ed ldi r16, 0xD8 ; 216 aec: 04 bf out 0x34, r16 ; 52 aee: 20 83 st Z, r18 : : "r" (tmpAddr), "r" (value), "M" (CCP_IOREG_gc), "i" (&CCP) : "r16", "r30", "r31" ); AVR_LEAVE_CRITICAL_REGION( ); af0: 89 81 ldd r24, Y+1 ; 0x01 af2: 8f bf out 0x3f, r24 ; 63 * is implemented for the XOSCF NMI when you enable it. */ void CLKSYS_XOSC_FailureDetection_Enable( void ) { CCPWrite( &OSC.XOSCFAIL, ( OSC_XOSCFDIF_bm | OSC_XOSCFDEN_bm ) ); } af4: 0f 90 pop r0 af6: cf 91 pop r28 af8: df 91 pop r29 afa: 0f 91 pop r16 afc: 08 95 ret 00000afe : * This will lock the configuration until the next reset, or until the * External Oscillator Failure Detections (XOSCFD) feature detects a failure * and switches to internal 2MHz RC oscillator. */ void CLKSYS_Configuration_Lock( void ) { afe: 0f 93 push r16 b00: df 93 push r29 b02: cf 93 push r28 b04: 0f 92 push r0 b06: cd b7 in r28, 0x3d ; 61 b08: de b7 in r29, 0x3e ; 62 // Restore global interrupt setting from scratch register. asm("out 0x3F, R1"); #elif defined __GNUC__ AVR_ENTER_CRITICAL_REGION( ); b0a: 8f b7 in r24, 0x3f ; 63 b0c: 89 83 std Y+1, r24 ; 0x01 b0e: f8 94 cli volatile uint8_t * tmpAddr = address; #ifdef RAMPZ RAMPZ = 0; b10: 1b be out 0x3b, r1 ; 59 #endif asm volatile( b12: 21 e0 ldi r18, 0x01 ; 1 b14: 82 e4 ldi r24, 0x42 ; 66 b16: 90 e0 ldi r25, 0x00 ; 0 b18: fc 01 movw r30, r24 b1a: 08 ed ldi r16, 0xD8 ; 216 b1c: 04 bf out 0x34, r16 ; 52 b1e: 20 83 st Z, r18 : : "r" (tmpAddr), "r" (value), "M" (CCP_IOREG_gc), "i" (&CCP) : "r16", "r30", "r31" ); AVR_LEAVE_CRITICAL_REGION( ); b20: 89 81 ldd r24, Y+1 ; 0x01 b22: 8f bf out 0x3f, r24 ; 63 * and switches to internal 2MHz RC oscillator. */ void CLKSYS_Configuration_Lock( void ) { CCPWrite( &CLK.LOCK, CLK_LOCK_bm ); } b24: 0f 90 pop r0 b26: cf 91 pop r28 b28: df 91 pop r29 b2a: 0f 91 pop r16 b2c: 08 95 ret 00000b2e : * * \param tc Timer/Counter module instance. * \param clockSelection Timer/Counter clock source setting. */ void TC0_ConfigClockSource( volatile TC0_t * tc, TC_CLKSEL_t clockSelection ) { b2e: fc 01 movw r30, r24 tc->CTRLA = ( tc->CTRLA & ~TC0_CLKSEL_gm ) | clockSelection; b30: 80 81 ld r24, Z b32: 80 7f andi r24, 0xF0 ; 240 b34: 86 2b or r24, r22 b36: 80 83 st Z, r24 } b38: 08 95 ret 00000b3a : * * \param tc Timer/Counter module instance. * \param clockSelection Timer/Counter clock source setting. */ void TC1_ConfigClockSource( volatile TC1_t * tc, TC_CLKSEL_t clockSelection ) { b3a: fc 01 movw r30, r24 tc->CTRLA = ( tc->CTRLA & ~TC1_CLKSEL_gm ) | clockSelection; b3c: 80 81 ld r24, Z b3e: 80 7f andi r24, 0xF0 ; 240 b40: 86 2b or r24, r22 b42: 80 83 st Z, r24 } b44: 08 95 ret 00000b46 : * * \param tc Timer/Counter module instance. * \param wgm Waveform generation mode. */ void TC0_ConfigWGM( volatile TC0_t * tc, TC_WGMODE_t wgm ) { b46: fc 01 movw r30, r24 tc->CTRLB = ( tc->CTRLB & ~TC0_WGMODE_gm ) | wgm; b48: 81 81 ldd r24, Z+1 ; 0x01 b4a: 88 7f andi r24, 0xF8 ; 248 b4c: 86 2b or r24, r22 b4e: 81 83 std Z+1, r24 ; 0x01 } b50: 08 95 ret 00000b52 : * * \param tc Timer/Counter module instance. * \param wgm Waveform generation mode. */ void TC1_ConfigWGM( volatile TC1_t * tc, TC_WGMODE_t wgm ) { b52: fc 01 movw r30, r24 tc->CTRLB = ( tc->CTRLB & ~TC1_WGMODE_gm ) | wgm; b54: 81 81 ldd r24, Z+1 ; 0x01 b56: 88 7f andi r24, 0xF8 ; 248 b58: 86 2b or r24, r22 b5a: 81 83 std Z+1, r24 ; 0x01 } b5c: 08 95 ret 00000b5e : * * \param tc Timer/Counter module instance. * \param eventSource Event source selection. */ void TC0_ConfigInputCapture( volatile TC0_t * tc, TC_EVSEL_t eventSource ) { b5e: fc 01 movw r30, r24 tc->CTRLD = ( tc->CTRLD & ~( TC0_EVSEL_gm | TC0_EVACT_gm ) ) | b60: 83 81 ldd r24, Z+3 ; 0x03 b62: 80 71 andi r24, 0x10 ; 16 b64: 80 62 ori r24, 0x20 ; 32 b66: 86 2b or r24, r22 b68: 83 83 std Z+3, r24 ; 0x03 eventSource | TC_EVACT_CAPT_gc; } b6a: 08 95 ret 00000b6c : * * \param tc Timer/Counter module instance. * \param eventSource Event source selection. */ void TC1_ConfigInputCapture( volatile TC1_t * tc, TC_EVSEL_t eventSource ) { b6c: fc 01 movw r30, r24 tc->CTRLD = ( tc->CTRLD & ~( TC1_EVSEL_gm | TC1_EVACT_gm ) ) | b6e: 83 81 ldd r24, Z+3 ; 0x03 b70: 80 71 andi r24, 0x10 ; 16 b72: 80 62 ori r24, 0x20 ; 32 b74: 86 2b or r24, r22 b76: 83 83 std Z+3, r24 ; 0x03 eventSource | TC_EVACT_CAPT_gc; } b78: 08 95 ret 00000b7a : * * \param tc Timer/Counter module instance. * \param enableMask Mask of channels to enable. */ void TC0_EnableCCChannels( volatile TC0_t * tc, uint8_t enableMask ) { b7a: fc 01 movw r30, r24 /* Make sure only CCxEN bits are set in enableMask. */ enableMask &= ( TC0_CCAEN_bm | TC0_CCBEN_bm | TC0_CCCEN_bm | TC0_CCDEN_bm ); /* Enable channels. */ tc->CTRLB |= enableMask; b7c: 81 81 ldd r24, Z+1 ; 0x01 b7e: 60 7f andi r22, 0xF0 ; 240 b80: 86 2b or r24, r22 b82: 81 83 std Z+1, r24 ; 0x01 } b84: 08 95 ret 00000b86 : * * \param tc Timer/Counter module instance. * \param enableMask Mask of channels to enable. */ void TC1_EnableCCChannels( volatile TC1_t * tc, uint8_t enableMask ) { b86: fc 01 movw r30, r24 /* Make sure only CCxEN bits are set in enableMask. */ enableMask &= ( TC1_CCAEN_bm | TC1_CCBEN_bm ); /* Enable channels. */ tc->CTRLB |= enableMask; b88: 81 81 ldd r24, Z+1 ; 0x01 b8a: 60 73 andi r22, 0x30 ; 48 b8c: 86 2b or r24, r22 b8e: 81 83 std Z+1, r24 ; 0x01 } b90: 08 95 ret 00000b92 : * * \param tc Timer/Counter module instance. * \param disableMask Mask of channels to disable. */ void TC0_DisableCCChannels( volatile TC0_t * tc, uint8_t disableMask ) { b92: fc 01 movw r30, r24 /* Make sure only CCxEN bits are set in disableMask. */ disableMask &= ( TC0_CCAEN_bm | TC0_CCBEN_bm | TC0_CCCEN_bm | TC0_CCDEN_bm ); /* Disable channels. */ tc->CTRLB &= ~disableMask; b94: 81 81 ldd r24, Z+1 ; 0x01 b96: 60 7f andi r22, 0xF0 ; 240 b98: 60 95 com r22 b9a: 86 23 and r24, r22 b9c: 81 83 std Z+1, r24 ; 0x01 } b9e: 08 95 ret 00000ba0 : * * \param tc Timer/Counter module instance. * \param disableMask Mask of channels to disable. */ void TC1_DisableCCChannels( volatile TC1_t * tc, uint8_t disableMask ) { ba0: fc 01 movw r30, r24 /* Make sure only CCxEN bits are set in disableMask. */ disableMask &= ( TC1_CCAEN_bm | TC1_CCBEN_bm ); /* Disable channels. */ tc->CTRLB &= ~disableMask; ba2: 81 81 ldd r24, Z+1 ; 0x01 ba4: 60 73 andi r22, 0x30 ; 48 ba6: 60 95 com r22 ba8: 86 23 and r24, r22 baa: 81 83 std Z+1, r24 ; 0x01 } bac: 08 95 ret 00000bae : * * \param tc Timer/Counter module instance. * \param intLevel New overflow interrupt level. */ void TC0_SetOverflowIntLevel( volatile TC0_t * tc, TC_OVFINTLVL_t intLevel ) { bae: fc 01 movw r30, r24 tc->INTCTRLA = ( tc->INTCTRLA & ~TC0_OVFINTLVL_gm ) | intLevel; bb0: 86 81 ldd r24, Z+6 ; 0x06 bb2: 8c 7f andi r24, 0xFC ; 252 bb4: 86 2b or r24, r22 bb6: 86 83 std Z+6, r24 ; 0x06 } bb8: 08 95 ret 00000bba : * * \param tc Timer/Counter module instance. * \param intLevel New overflow interrupt level. */ void TC1_SetOverflowIntLevel( volatile TC1_t * tc, TC_OVFINTLVL_t intLevel ) { bba: fc 01 movw r30, r24 tc->INTCTRLA = ( tc->INTCTRLA & ~TC1_OVFINTLVL_gm ) | intLevel; bbc: 86 81 ldd r24, Z+6 ; 0x06 bbe: 8c 7f andi r24, 0xFC ; 252 bc0: 86 2b or r24, r22 bc2: 86 83 std Z+6, r24 ; 0x06 } bc4: 08 95 ret 00000bc6 : * * \param tc Timer/Counter module instance. * \param intLevel New error interrupt level. */ void TC0_SetErrorIntLevel( volatile TC0_t * tc, TC_ERRINTLVL_t intLevel ) { bc6: fc 01 movw r30, r24 tc->INTCTRLA = ( tc->INTCTRLA & ~TC0_ERRINTLVL_gm ) | intLevel; bc8: 86 81 ldd r24, Z+6 ; 0x06 bca: 83 7f andi r24, 0xF3 ; 243 bcc: 86 2b or r24, r22 bce: 86 83 std Z+6, r24 ; 0x06 } bd0: 08 95 ret 00000bd2 : * * \param tc Timer/Counter module instance. * \param intLevel New error interrupt level. */ void TC1_SetErrorIntLevel( volatile TC1_t * tc, TC_ERRINTLVL_t intLevel ) { bd2: fc 01 movw r30, r24 tc->INTCTRLA = ( tc->INTCTRLA & ~TC1_ERRINTLVL_gm ) | intLevel; bd4: 86 81 ldd r24, Z+6 ; 0x06 bd6: 83 7f andi r24, 0xF3 ; 243 bd8: 86 2b or r24, r22 bda: 86 83 std Z+6, r24 ; 0x06 } bdc: 08 95 ret 00000bde : * * \param tc Timer/Counter module instance. * \param intLevel New compare/capture channel A interrupt level. */ void TC0_SetCCAIntLevel( volatile TC0_t * tc, TC_CCAINTLVL_t intLevel ) { bde: fc 01 movw r30, r24 tc->INTCTRLB = ( tc->INTCTRLB & ~TC0_CCAINTLVL_gm ) | intLevel; be0: 87 81 ldd r24, Z+7 ; 0x07 be2: 8c 7f andi r24, 0xFC ; 252 be4: 86 2b or r24, r22 be6: 87 83 std Z+7, r24 ; 0x07 } be8: 08 95 ret 00000bea : * * \param tc Timer/Counter module instance. * \param intLevel New compare/capture channel A interrupt level. */ void TC1_SetCCAIntLevel( volatile TC1_t * tc, TC_CCAINTLVL_t intLevel ) { bea: fc 01 movw r30, r24 tc->INTCTRLB = ( tc->INTCTRLB & ~TC1_CCAINTLVL_gm ) | intLevel; bec: 87 81 ldd r24, Z+7 ; 0x07 bee: 8c 7f andi r24, 0xFC ; 252 bf0: 86 2b or r24, r22 bf2: 87 83 std Z+7, r24 ; 0x07 } bf4: 08 95 ret 00000bf6 : * * \param tc Timer/Counter module instance. * \param intLevel New compare/capture channel B interrupt level. */ void TC0_SetCCBIntLevel( volatile TC0_t * tc, TC_CCBINTLVL_t intLevel ) { bf6: fc 01 movw r30, r24 tc->INTCTRLB = ( tc->INTCTRLB & ~TC0_CCBINTLVL_gm ) | intLevel; bf8: 87 81 ldd r24, Z+7 ; 0x07 bfa: 83 7f andi r24, 0xF3 ; 243 bfc: 86 2b or r24, r22 bfe: 87 83 std Z+7, r24 ; 0x07 } c00: 08 95 ret 00000c02 : * * \param tc Timer/Counter module instance. * \param intLevel New compare/capture channel B interrupt level. */ void TC1_SetCCBIntLevel( volatile TC1_t * tc, TC_CCBINTLVL_t intLevel ) { c02: fc 01 movw r30, r24 tc->INTCTRLB = ( tc->INTCTRLB & ~TC1_CCBINTLVL_gm ) | intLevel; c04: 87 81 ldd r24, Z+7 ; 0x07 c06: 83 7f andi r24, 0xF3 ; 243 c08: 86 2b or r24, r22 c0a: 87 83 std Z+7, r24 ; 0x07 } c0c: 08 95 ret 00000c0e : * * \param tc Timer/Counter module instance. * \param intLevel New compare/capture channel A interrupt level. */ void TC0_SetCCCIntLevel( volatile TC0_t * tc, TC_CCCINTLVL_t intLevel ) { c0e: fc 01 movw r30, r24 tc->INTCTRLB = ( tc->INTCTRLB & ~TC0_CCCINTLVL_gm ) | intLevel; c10: 87 81 ldd r24, Z+7 ; 0x07 c12: 8f 7c andi r24, 0xCF ; 207 c14: 86 2b or r24, r22 c16: 87 83 std Z+7, r24 ; 0x07 } c18: 08 95 ret 00000c1a : * * \param tc Timer/Counter module instance. * \param intLevel New compare/capture channel A interrupt level. */ void TC0_SetCCDIntLevel( volatile TC0_t * tc, TC_CCDINTLVL_t intLevel ) { c1a: fc 01 movw r30, r24 tc->INTCTRLB = ( tc->INTCTRLB & ~TC0_CCDINTLVL_gm ) | intLevel; c1c: 87 81 ldd r24, Z+7 ; 0x07 c1e: 8f 73 andi r24, 0x3F ; 63 c20: 86 2b or r24, r22 c22: 87 83 std Z+7, r24 ; 0x07 } c24: 08 95 ret 00000c26 : * reset of the device. * * \param tc Timer/Counter 0 module instance. */ void TC0_Reset( volatile TC0_t * tc ) { c26: fc 01 movw r30, r24 /* TC must be turned off before a Reset command. */ tc->CTRLA = ( tc->CTRLA & ~TC0_CLKSEL_gm ) | TC_CLKSEL_OFF_gc; c28: 80 81 ld r24, Z c2a: 80 7f andi r24, 0xF0 ; 240 c2c: 80 83 st Z, r24 /* Issue Reset command. */ tc->CTRLFSET = TC_CMD_RESET_gc; c2e: 8c e0 ldi r24, 0x0C ; 12 c30: 81 87 std Z+9, r24 ; 0x09 } c32: 08 95 ret 00000c34 : * reset of the device. * * \param tc Timer/Counter 1 module instance. */ void TC1_Reset( volatile TC1_t * tc ) { c34: fc 01 movw r30, r24 /* TC must be turned off before a Reset command. */ tc->CTRLA = ( tc->CTRLA & ~TC1_CLKSEL_gm ) | TC_CLKSEL_OFF_gc; c36: 80 81 ld r24, Z c38: 80 7f andi r24, 0xF0 ; 240 c3a: 80 83 st Z, r24 /* Issue Reset command. */ tc->CTRLFSET = TC_CMD_RESET_gc; c3c: 8c e0 ldi r24, 0x0C ; 12 c3e: 81 87 std Z+9, r24 ; 0x09 } c40: 08 95 ret 00000c42 <_exit>: c42: f8 94 cli 00000c44 <__stop_program>: c44: ff cf rjmp .-2 ; 0xc44 <__stop_program>