;-------------------------------------------------------- ; File Created by SDCC : free open source ANSI-C Compiler ; Version 3.0.1 #6101 (Jan 12 2011) (Linux) ; This file was generated Sun Jan 16 16:43:00 2011 ;-------------------------------------------------------- ; PIC16 port for the Microchip 16-bit core micros ;-------------------------------------------------------- list p=18f2680 __config 0x300001, 0xf2 __config 0x300003, 0xfe __config 0x300006, 0xbb radix dec ;-------------------------------------------------------- ; public variables in this module ;-------------------------------------------------------- global _CAN_status_ptr global _pt global _ui global _TIMER_setup global _TIMER_set_T0 global _TIMER_set_T1 global _TIMER_set_T2 global _TIMER_get global _CAN_init global _CAN_recv global _CAN_send global _CAN_setFilters global _HAL_read_eeprom_byte global _HAL_write_eeprom_byte global _SERIAL_initialize global _SERIAL_putc global _SERIAL_getc global _SERIAL_write global _SERIAL_readable global _SERIAL_writable global _HAL_INT_TIMER0_FUNC global _CAN_status1 global _rxdata global _CAN_runOnce global _INTERRUPTS_init global _INTERRUPTS_runOnce global _main ;-------------------------------------------------------- ; extern variables in this module ;-------------------------------------------------------- extern __gptrget1 extern __gptrput2 extern __gptrget2 extern __gptrput1 extern _RXF6SIDHbits extern _RXF6SIDLbits extern _RXF6EIDHbits extern _RXF6EIDLbits extern _RXF7SIDHbits extern _RXF7SIDLbits extern _RXF7EIDHbits extern _RXF7EIDLbits extern _RXF8SIDHbits extern _RXF8SIDLbits extern _RXF8EIDHbits extern _RXF8EIDLbits extern _RXF9SIDHbits extern _RXF9SIDLbits extern _RXF9EIDHbits extern _RXF9EIDLbits extern _RXF10SIDHbits extern _RXF10SIDLbits extern _RXF10EIDHbits extern _RXF10EIDLbits extern _RXF11SIDHbits extern _RXF11SIDLbits extern _RXF11EIDHbits extern _RXF11EIDLbits extern _RXF12SIDHbits extern _RXF12SIDLbits extern _RXF12EIDHbits extern _RXF12EIDLbits extern _RXF13SIDHbits extern _RXF13SIDLbits extern _RXF13EIDHbits extern _RXF13EIDLbits extern _RXF14SIDHbits extern _RXF14SIDLbits extern _RXF14EIDHbits extern _RXF14EIDLbits extern _RXF15SIDHbits extern _RXF15SIDLbits extern _RXF15EIDHbits extern _RXF15EIDLbits extern _RXFCON0bits extern _RXFCON1bits extern _SDFLCbits extern _RXFBCON0bits extern _RXFBCON1bits extern _RXFBCON2bits extern _RXFBCON3bits extern _RXFBCON4bits extern _RXFBCON5bits extern _RXFBCON6bits extern _RXFBCON7bits extern _MSEL0bits extern _MSEL1bits extern _MSEL2bits extern _MSEL3bits extern _BSEL0bits extern _BIE0bits extern _TXBIEbits extern _B0CONbits extern _B0SIDHbits extern _B0SIDLbits extern _B0EIDHbits extern _B0EIDLbits extern _B0DLCbits extern _B0D0bits extern _B0D1bits extern _B0D2bits extern _B0D3bits extern _B0D4bits extern _B0D5bits extern _B0D6bits extern _B0D7bits extern _CANSTAT_RO9bits extern _CANCON_RO9bits extern _B1CONbits extern _B1SIDHbits extern _B1SIDLbits extern _B1EIDHbits extern _B1EIDLbits extern _B1DLCbits extern _B1D0bits extern _B1D1bits extern _B1D2bits extern _B1D3bits extern _B1D4bits extern _B1D5bits extern _B1D6bits extern _B1D7bits extern _CANSTAT_RO8bits extern _CANCON_RO8bits extern _B2CONbits extern _B2SIDHbits extern _B2SIDLbits extern _B2EIDHbits extern _B2EIDLbits extern _B2DLCbits extern _B2D0bits extern _B2D1bits extern _B2D2bits extern _B2D3bits extern _B2D4bits extern _B2D5bits extern _B2D6bits extern _B2D7bits extern _CANSTAT_RO7bits extern _CANCON_RO7bits extern _B3CONbits extern _B3SIDHbits extern _B3SIDLbits extern _B3EIDHbits extern _B3EIDLbits extern _B3DLCbits extern _B3D0bits extern _B3D1bits extern _B3D2bits extern _B3D3bits extern _B3D4bits extern _B3D5bits extern _B3D6bits extern _B3D7bits extern _CANSTAT_RO6bits extern _CANCON_RO6bits extern _B4CONbits extern _B4SIDHbits extern _B4SIDLbits extern _B4EIDHbits extern _B4EIDLbits extern _B4DLCbits extern _B4D0bits extern _B4D1bits extern _B4D2bits extern _B4D3bits extern _B4D4bits extern _B4D5bits extern _B4D6bits extern _B4D7bits extern _CANSTAT_RO5bits extern _CANCON_RO5bits extern _B5CONbits extern _B5SIDHbits extern _B5SIDLbits extern _B5EIDHbits extern _B5EIDLbits extern _B5DLCbits extern _B5D0bits extern _B5D1bits extern _B5D2bits extern _B5D3bits extern _B5D4bits extern _B5D5bits extern _B5D6bits extern _B5D7bits extern _CANSTAT_RO4bits extern _CANCON_RO4bits extern _RXF0SIDHbits extern _RXF0SIDLbits extern _RXF0EIDHbits extern _RXF0EIDLbits extern _RXF1SIDHbits extern _RXF1SIDLbits extern _RXF1EIDHbits extern _RXF1EIDLbits extern _RXF2SIDHbits extern _RXF2SIDLbits extern _RXF2EIDHbits extern _RXF2EIDLbits extern _RXF3SIDHbits extern _RXF3SIDLbits extern _RXF3EIDHbits extern _RXF3EIDLbits extern _RXF4SIDHbits extern _RXF4SIDLbits extern _RXF4EIDHbits extern _RXF4EIDLbits extern _RXF5SIDHbits extern _RXF5SIDLbits extern _RXF5EIDHbits extern _RXF5EIDLbits extern _RXM0SIDHbits extern _RXM0SIDLbits extern _RXM0EIDHbits extern _RXM0EIDLbits extern _RXM1SIDHbits extern _RXM1SIDLbits extern _RXM1EIDHbits extern _RXM1EIDLbits extern _TXB2CONbits extern _TXB2SIDHbits extern _TXB2SIDLbits extern _TXB2EIDHbits extern _TXB2EIDLbits extern _TXB2DLCbits extern _TXB2D0bits extern _TXB2D1bits extern _TXB2D2bits extern _TXB2D3bits extern _TXB2D4bits extern _TXB2D5bits extern _TXB2D6bits extern _TXB2D7bits extern _CANSTAT_RO3bits extern _CANCON_RO3bits extern _TXB1CONbits extern _TXB1SIDHbits extern _TXB1SIDLbits extern _TXB1EIDHbits extern _TXB1EIDLbits extern _TXB1DLCbits extern _TXB1D0bits extern _TXB1D1bits extern _TXB1D2bits extern _TXB1D3bits extern _TXB1D4bits extern _TXB1D5bits extern _TXB1D6bits extern _TXB1D7bits extern _CANSTAT_RO2bits extern _CANCON_RO2bits extern _TXB0CONbits extern _TXB0SIDHbits extern _TXB0SIDLbits extern _TXB0EIDHbits extern _TXB0EIDLbits extern _TXB0DLCbits extern _TXB0D0bits extern _TXB0D1bits extern _TXB0D2bits extern _TXB0D3bits extern _TXB0D4bits extern _TXB0D5bits extern _TXB0D6bits extern _TXB0D7bits extern _CANSTAT_RO1bits extern _CANCON_RO1bits extern _RXB1CONbits extern _RXB1SIDHbits extern _RXB1SIDLbits extern _RXB1EIDHbits extern _RXB1EIDLbits extern _RXB1DLCbits extern _RXB1D0bits extern _RXB1D1bits extern _RXB1D2bits extern _RXB1D3bits extern _RXB1D4bits extern _RXB1D5bits extern _RXB1D6bits extern _RXB1D7bits extern _CANSTAT_RO0bits extern _CANCON_RO0bits extern _RXB0CONbits extern _RXB0SIDHbits extern _RXB0SIDLbits extern _RXB0EIDHbits extern _RXB0EIDLbits extern _RXB0DLCbits extern _RXB0D0bits extern _RXB0D1bits extern _RXB0D2bits extern _RXB0D3bits extern _RXB0D4bits extern _RXB0D5bits extern _RXB0D6bits extern _RXB0D7bits extern _CANSTATbits extern _CANCONbits extern _BRGCON1bits extern _BRGCON2bits extern _BRGCON3bits extern _CIOCONbits extern _COMSTATbits extern _RXERRCNTbits extern _TXERRCNTbits extern _ECANCONbits extern _PORTAbits extern _PORTBbits extern _PORTCbits extern _LATAbits extern _LATBbits extern _LATCbits extern _DDRAbits extern _TRISAbits extern _DDRBbits extern _TRISBbits extern _DDRCbits extern _TRISCbits extern _OSCTUNEbits extern _PIE1bits extern _PIR1bits extern _IPR1bits extern _PIE2bits extern _PIR2bits extern _IPR2bits extern _PIE3bits extern _PIR3bits extern _IPR3bits extern _EECON1bits extern _RCSTAbits extern _TXSTAbits extern _T3CONbits extern _BAUDCONbits extern _CCP1CONbits extern _ADCON2bits extern _ADCON1bits extern _ADCON0bits extern _SSPCON2bits extern _SSPCON1bits extern _SSPSTATbits extern _T2CONbits extern _T1CONbits extern _RCONbits extern _WDTCONbits extern _HLVDCONbits extern _LVDCONbits extern _OSCCONbits extern _T0CONbits extern _STATUSbits extern _INTCON3bits extern _INTCON2bits extern _INTCONbits extern _STKPTRbits extern __ECANRxFilterHitInfo extern _RXF6SIDH extern _RXF6SIDL extern _RXF6EIDH extern _RXF6EIDL extern _RXF7SIDH extern _RXF7SIDL extern _RXF7EIDH extern _RXF7EIDL extern _RXF8SIDH extern _RXF8SIDL extern _RXF8EIDH extern _RXF8EIDL extern _RXF9SIDH extern _RXF9SIDL extern _RXF9EIDH extern _RXF9EIDL extern _RXF10SIDH extern _RXF10SIDL extern _RXF10EIDH extern _RXF10EIDL extern _RXF11SIDH extern _RXF11SIDL extern _RXF11EIDH extern _RXF11EIDL extern _RXF12SIDH extern _RXF12SIDL extern _RXF12EIDH extern _RXF12EIDL extern _RXF13SIDH extern _RXF13SIDL extern _RXF13EIDH extern _RXF13EIDL extern _RXF14SIDH extern _RXF14SIDL extern _RXF14EIDH extern _RXF14EIDL extern _RXF15SIDH extern _RXF15SIDL extern _RXF15EIDH extern _RXF15EIDL extern _RXFCON0 extern _RXFCON1 extern _SDFLC extern _RXFBCON0 extern _RXFBCON1 extern _RXFBCON2 extern _RXFBCON3 extern _RXFBCON4 extern _RXFBCON5 extern _RXFBCON6 extern _RXFBCON7 extern _MSEL0 extern _MSEL1 extern _MSEL2 extern _MSEL3 extern _BSEL0 extern _BIE0 extern _TXBIE extern _B0CON extern _B0SIDH extern _B0SIDL extern _B0EIDH extern _B0EIDL extern _B0DLC extern _B0D0 extern _B0D1 extern _B0D2 extern _B0D3 extern _B0D4 extern _B0D5 extern _B0D6 extern _B0D7 extern _CANSTAT_RO9 extern _CANCON_RO9 extern _B1CON extern _B1SIDH extern _B1SIDL extern _B1EIDH extern _B1EIDL extern _B1DLC extern _B1D0 extern _B1D1 extern _B1D2 extern _B1D3 extern _B1D4 extern _B1D5 extern _B1D6 extern _B1D7 extern _CANSTAT_RO8 extern _CANCON_RO8 extern _B2CON extern _B2SIDH extern _B2SIDL extern _B2EIDH extern _B2EIDL extern _B2DLC extern _B2D0 extern _B2D1 extern _B2D2 extern _B2D3 extern _B2D4 extern _B2D5 extern _B2D6 extern _B2D7 extern _CANSTAT_RO7 extern _CANCON_RO7 extern _B3CON extern _B3SIDH extern _B3SIDL extern _B3EIDH extern _B3EIDL extern _B3DLC extern _B3D0 extern _B3D1 extern _B3D2 extern _B3D3 extern _B3D4 extern _B3D5 extern _B3D6 extern _B3D7 extern _CANSTAT_RO6 extern _CANCON_RO6 extern _B4CON extern _B4SIDH extern _B4SIDL extern _B4EIDH extern _B4EIDL extern _B4DLC extern _B4D0 extern _B4D1 extern _B4D2 extern _B4D3 extern _B4D4 extern _B4D5 extern _B4D6 extern _B4D7 extern _CANSTAT_RO5 extern _CANCON_RO5 extern _B5CON extern _B5SIDH extern _B5SIDL extern _B5EIDH extern _B5EIDL extern _B5DLC extern _B5D0 extern _B5D1 extern _B5D2 extern _B5D3 extern _B5D4 extern _B5D5 extern _B5D6 extern _B5D7 extern _CANSTAT_RO4 extern _CANCON_RO4 extern _RXF0SIDH extern _RXF0SIDL extern _RXF0EIDH extern _RXF0EIDL extern _RXF1SIDH extern _RXF1SIDL extern _RXF1EIDH extern _RXF1EIDL extern _RXF2SIDH extern _RXF2SIDL extern _RXF2EIDH extern _RXF2EIDL extern _RXF3SIDH extern _RXF3SIDL extern _RXF3EIDH extern _RXF3EIDL extern _RXF4SIDH extern _RXF4SIDL extern _RXF4EIDH extern _RXF4EIDL extern _RXF5SIDH extern _RXF5SIDL extern _RXF5EIDH extern _RXF5EIDL extern _RXM0SIDH extern _RXM0SIDL extern _RXM0EIDH extern _RXM0EIDL extern _RXM1SIDH extern _RXM1SIDL extern _RXM1EIDH extern _RXM1EIDL extern _TXB2CON extern _TXB2SIDH extern _TXB2SIDL extern _TXB2EIDH extern _TXB2EIDL extern _TXB2DLC extern _TXB2D0 extern _TXB2D1 extern _TXB2D2 extern _TXB2D3 extern _TXB2D4 extern _TXB2D5 extern _TXB2D6 extern _TXB2D7 extern _CANSTAT_RO3 extern _CANCON_RO3 extern _TXB1CON extern _TXB1SIDH extern _TXB1SIDL extern _TXB1EIDH extern _TXB1EIDL extern _TXB1DLC extern _TXB1D0 extern _TXB1D1 extern _TXB1D2 extern _TXB1D3 extern _TXB1D4 extern _TXB1D5 extern _TXB1D6 extern _TXB1D7 extern _CANSTAT_RO2 extern _CANCON_RO2 extern _TXB0CON extern _TXB0SIDH extern _TXB0SIDL extern _TXB0EIDH extern _TXB0EIDL extern _TXB0DLC extern _TXB0D0 extern _TXB0D1 extern _TXB0D2 extern _TXB0D3 extern _TXB0D4 extern _TXB0D5 extern _TXB0D6 extern _TXB0D7 extern _CANSTAT_RO1 extern _CANCON_RO1 extern _RXB1CON extern _RXB1SIDH extern _RXB1SIDL extern _RXB1EIDH extern _RXB1EIDL extern _RXB1DLC extern _RXB1D0 extern _RXB1D1 extern _RXB1D2 extern _RXB1D3 extern _RXB1D4 extern _RXB1D5 extern _RXB1D6 extern _RXB1D7 extern _CANSTAT_RO0 extern _CANCON_RO0 extern _RXB0CON extern _RXB0SIDH extern _RXB0SIDL extern _RXB0EIDH extern _RXB0EIDL extern _RXB0DLC extern _RXB0D0 extern _RXB0D1 extern _RXB0D2 extern _RXB0D3 extern _RXB0D4 extern _RXB0D5 extern _RXB0D6 extern _RXB0D7 extern _CANSTAT extern _CANCON extern _BRGCON1 extern _BRGCON2 extern _BRGCON3 extern _CIOCON extern _COMSTAT extern _RXERRCNT extern _TXERRCNT extern _ECANCON extern _PORTA extern _PORTB extern _PORTC extern _LATA extern _LATB extern _LATC extern _DDRA extern _TRISA extern _DDRB extern _TRISB extern _DDRC extern _TRISC extern _OSCTUNE extern _PIE1 extern _PIR1 extern _IPR1 extern _PIE2 extern _PIR2 extern _IPR2 extern _PIE3 extern _PIR3 extern _IPR3 extern _EECON1 extern _EECON2 extern _EEDATA extern _EEADR extern _EEADRH extern _RCSTA extern _TXSTA extern _TXREG extern _RCREG extern _SPBRG extern _SPBRGH extern _T3CON extern _TMR3L extern _TMR3H extern _BAUDCON extern _CCP1CON extern _CCPR1 extern _CCPR1L extern _CCPR1H extern _ADCON2 extern _ADCON1 extern _ADCON0 extern _ADRES extern _ADRESL extern _ADRESH extern _SSPCON2 extern _SSPCON1 extern _SSPSTAT extern _SSPADD extern _SSPBUF extern _T2CON extern _PR2 extern _TMR2 extern _T1CON extern _TMR1L extern _TMR1H extern _RCON extern _WDTCON extern _HLVDCON extern _LVDCON extern _OSCCON extern _T0CON extern _TMR0L extern _TMR0H extern _STATUS extern _FSR2L extern _FSR2H extern _PLUSW2 extern _PREINC2 extern _POSTDEC2 extern _POSTINC2 extern _INDF2 extern _BSR extern _FSR1L extern _FSR1H extern _PLUSW1 extern _PREINC1 extern _POSTDEC1 extern _POSTINC1 extern _INDF1 extern _WREG extern _FSR0L extern _FSR0H extern _PLUSW0 extern _PREINC0 extern _POSTDEC0 extern _POSTINC0 extern _INDF0 extern _INTCON3 extern _INTCON2 extern _INTCON extern _PROD extern _PRODL extern _PRODH extern _TABLAT extern _TBLPTR extern _TBLPTRL extern _TBLPTRH extern _TBLPTRU extern _PC extern _PCL extern _PCLATH extern _PCLATU extern _STKPTR extern _TOS extern _TOSL extern _TOSH extern _TOSU extern _usart_open extern _usart_busy extern _usart_getc extern _usart_putc extern _ECANInitialize extern _ECANSendMessage extern _ECANReceiveMessage extern _ECANSetOperationMode extern __CANIDToRegs extern __mulint extern __divslong ;-------------------------------------------------------- ; Equates to used internal registers ;-------------------------------------------------------- STATUS equ 0xfd8 PCL equ 0xff9 PCLATH equ 0xffa PCLATU equ 0xffb WREG equ 0xfe8 BSR equ 0xfe0 FSR0L equ 0xfe9 FSR0H equ 0xfea FSR1L equ 0xfe1 FSR2L equ 0xfd9 INDF0 equ 0xfef POSTDEC1 equ 0xfe5 PREINC1 equ 0xfe4 PLUSW2 equ 0xfdb PRODL equ 0xff3 PRODH equ 0xff4 idata _ui db 0x61 _pt db LOW(_ui), HIGH(_ui), 0x80 _CAN_status_ptr db LOW(_CAN_status1), HIGH(_CAN_status1), 0x80 _CAN_send_rr_1_1 db 0x00 _CAN_setFilters_fltId_1_1 db 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 _rxdata db 0xaa ; Internal registers .registers udata_ovr 0x0000 r0x00 res 1 r0x01 res 1 r0x02 res 1 r0x03 res 1 r0x04 res 1 r0x05 res 1 r0x06 res 1 r0x07 res 1 r0x08 res 1 r0x09 res 1 r0x0a res 1 r0x0b res 1 r0x0c res 1 r0x0d res 1 r0x0e res 1 r0x0f res 1 r0x10 res 1 r0x11 res 1 udata_jgjh_0 udata _CAN_status1 res 5 udata_jgjh_1 udata _CAN_recv_temp_1_1 res 4 udata_jgjh_2 udata _CAN_recv_flags_1_1 res 1 udata_jgjh_3 udata _main_tcon_1_1 res 2 udata_jgjh_4 udata _main_serial_setting_1_1 res 6 udata_jgjh_5 udata _main_spi_setting_1_1 res 6 ;-------------------------------------------------------- ; interrupt vector ;-------------------------------------------------------- ;-------------------------------------------------------- ; global & static initialisations ;-------------------------------------------------------- ; ; Starting pCode block for absolute section ; ;----------------------------------------- S_jgjh_ivec_0x1_isr code 0X000008 ivec_0x1_isr: GOTO _isr ; I code from now on! ; ; Starting pCode block S_jgjh__main code _main: BANKSEL _main_tcon_1_1 ; .line 24; jgjh.c struct TIMER_config tcon = {0,6}; CLRF _main_tcon_1_1, B MOVLW 0x06 BANKSEL (_main_tcon_1_1 + 1) MOVWF (_main_tcon_1_1 + 1), B BANKSEL _main_serial_setting_1_1 ; .line 28; jgjh.c serial_setting.baud = 57600; CLRF _main_serial_setting_1_1, B MOVLW 0xe1 BANKSEL (_main_serial_setting_1_1 + 1) MOVWF (_main_serial_setting_1_1 + 1), B ; .line 29; jgjh.c serial_setting.stopbit = 1; MOVLW 0x01 BANKSEL (_main_serial_setting_1_1 + 3) MOVWF (_main_serial_setting_1_1 + 3), B ; .line 31; jgjh.c spi_setting.mstr_slv = 1; // set Master MOVLW 0x01 BANKSEL (_main_spi_setting_1_1 + 4) MOVWF (_main_spi_setting_1_1 + 4), B ; .line 34; jgjh.c SERIAL_initialize(uart, &serial_setting); MOVLW HIGH(_main_serial_setting_1_1) MOVWF r0x01 MOVLW LOW(_main_serial_setting_1_1) MOVWF r0x00 MOVLW 0x80 MOVWF r0x02 MOVF r0x02, W MOVWF POSTDEC1 MOVF r0x01, W MOVWF POSTDEC1 MOVF r0x00, W MOVWF POSTDEC1 MOVLW 0x00 MOVWF POSTDEC1 MOVLW 0x00 MOVWF POSTDEC1 CALL _SERIAL_initialize MOVLW 0x05 ADDWF FSR1L, F ; .line 35; jgjh.c SERIAL_initialize(spi, &spi_setting); MOVLW HIGH(_main_spi_setting_1_1) MOVWF r0x01 MOVLW LOW(_main_spi_setting_1_1) MOVWF r0x00 MOVLW 0x80 MOVWF r0x02 MOVF r0x02, W MOVWF POSTDEC1 MOVF r0x01, W MOVWF POSTDEC1 MOVF r0x00, W MOVWF POSTDEC1 MOVLW 0x00 MOVWF POSTDEC1 MOVLW 0x01 MOVWF POSTDEC1 CALL _SERIAL_initialize MOVLW 0x05 ADDWF FSR1L, F ; .line 38; jgjh.c TIMER_setup(tim,&tcon); MOVLW HIGH(_main_tcon_1_1) MOVWF r0x01 MOVLW LOW(_main_tcon_1_1) MOVWF r0x00 MOVLW 0x80 MOVWF r0x02 MOVF r0x02, W MOVWF POSTDEC1 MOVF r0x01, W MOVWF POSTDEC1 MOVF r0x00, W MOVWF POSTDEC1 MOVLW 0x00 MOVWF POSTDEC1 CALL _TIMER_setup MOVLW 0x04 ADDWF FSR1L, F ; .line 41; jgjh.c INTERRUPTS_init(); CALL _INTERRUPTS_init ; .line 43; jgjh.c TRISB = TRISB & 0xfc; // set pin B1 & B0 to output MOVLW 0xfc ANDWF _TRISB, F ; .line 44; jgjh.c LATBbits.LATB1 = 1; BSF _LATBbits, 1 ; .line 45; jgjh.c LATBbits.LATB0 = 0; BCF _LATBbits, 0 ; .line 57; jgjh.c while(1) CLRF WREG CLRF WREG MOVLW 0x01 MOVWF r0x00 CLRF r0x01 _00414_DS_: ; .line 62; jgjh.c if(SERIAL_readable(spi)) // check if data has been received MOVLW 0x00 MOVWF POSTDEC1 MOVLW 0x01 MOVWF POSTDEC1 CALL _SERIAL_readable MOVWF r0x02 MOVLW 0x02 ADDWF FSR1L, F MOVF r0x02, W BZ _00407_DS_ ; .line 64; jgjh.c rxdata = SERIAL_getc(spi); MOVLW 0x00 MOVWF POSTDEC1 MOVLW 0x01 MOVWF POSTDEC1 CALL _SERIAL_getc BANKSEL _rxdata MOVWF _rxdata, B MOVLW 0x02 ADDWF FSR1L, F BANKSEL _rxdata ; .line 65; jgjh.c SERIAL_putc(uart,rxdata); MOVF _rxdata, W, B MOVWF POSTDEC1 MOVLW 0x00 MOVWF POSTDEC1 MOVLW 0x00 MOVWF POSTDEC1 CALL _SERIAL_putc MOVLW 0x03 ADDWF FSR1L, F _00407_DS_: ; .line 72; jgjh.c if(SERIAL_readable(uart) == 1) MOVLW 0x00 MOVWF POSTDEC1 MOVLW 0x00 MOVWF POSTDEC1 CALL _SERIAL_readable MOVWF r0x02 MOVLW 0x02 ADDWF FSR1L, F MOVF r0x02, W XORLW 0x01 BNZ _00409_DS_ ; .line 75; jgjh.c temp = SERIAL_getc(uart); MOVLW 0x00 MOVWF POSTDEC1 MOVLW 0x00 MOVWF POSTDEC1 CALL _SERIAL_getc MOVWF r0x02 MOVLW 0x02 ADDWF FSR1L, F ; .line 78; jgjh.c SERIAL_putc(spi,temp); MOVF r0x02, W MOVWF POSTDEC1 MOVLW 0x00 MOVWF POSTDEC1 MOVLW 0x01 MOVWF POSTDEC1 CALL _SERIAL_putc MOVLW 0x03 ADDWF FSR1L, F _00409_DS_: ; .line 83; jgjh.c ACK++; INCF r0x00, F BTFSC STATUS, 0 INCF r0x01, F ; .line 84; jgjh.c if(ACK>15000) MOVF r0x01, W ADDLW 0x80 ADDLW 0x46 BNZ _00425_DS_ MOVLW 0x99 SUBWF r0x00, W _00425_DS_: BNC _00411_DS_ ; .line 86; jgjh.c LATBbits.LATB0 = 1; BSF _LATBbits, 0 BRA _00414_DS_ _00411_DS_: ; .line 91; jgjh.c LATBbits.LATB0 = 0; BCF _LATBbits, 0 BRA _00414_DS_ RETURN ; ; Starting pCode block S_jgjh__HAL_INT_TIMER0_FUNC code _HAL_INT_TIMER0_FUNC: ; .line 100; jgjh.c void HAL_INT_TIMER0_FUNC() MOVFF FSR2L, POSTDEC1 MOVFF FSR1L, FSR2L ; .line 103; jgjh.c } MOVFF PREINC1, FSR2L RETURN ; ; Starting pCode block S_jgjh__INTERRUPTS_runOnce code _INTERRUPTS_runOnce: ; .line 70; interrupts.c void INTERRUPTS_runOnce( void ){} MOVFF FSR2L, POSTDEC1 MOVFF FSR1L, FSR2L MOVFF PREINC1, FSR2L RETURN ; ; Starting pCode block S_jgjh__INTERRUPTS_init code _INTERRUPTS_init: ; .line 40; interrupts.c int INTERRUPTS_init(void){ MOVFF FSR2L, POSTDEC1 MOVFF FSR1L, FSR2L ; .line 55; interrupts.c INTCONbits.TMR0IE = 1; // enable timer 0 interrupts BSF _INTCONbits, 5 ; .line 56; interrupts.c INTCON2bits.TMR0IP = 1; // set high priority BSF _INTCON2bits, 2 ; .line 66; interrupts.c INTCONbits.GIEH = 1; //enable global interrupts BSF _INTCONbits, 7 ; .line 67; interrupts.c return i; CLRF PRODL MOVLW 0x01 MOVFF PREINC1, FSR2L RETURN ; ; Starting pCode block S_jgjh__isr code _isr: ; .line 18; interrupts.c static void isr(void) __interrupt 1 MOVFF WREG, POSTDEC1 MOVFF STATUS, POSTDEC1 MOVFF BSR, POSTDEC1 MOVFF PRODL, POSTDEC1 MOVFF PRODH, POSTDEC1 MOVFF FSR0L, POSTDEC1 MOVFF FSR0H, POSTDEC1 MOVFF PCLATH, POSTDEC1 MOVFF PCLATU, POSTDEC1 MOVFF FSR2L, POSTDEC1 MOVFF FSR1L, FSR2L MOVFF r0x00, POSTDEC1 ; .line 31; interrupts.c if(INTCONbits.TMR0IF==1) CLRF r0x00 BTFSC _INTCONbits, 2 INCF r0x00, F MOVF r0x00, W XORLW 0x01 BNZ _00387_DS_ ; .line 33; interrupts.c HAL_INT_TIMER0_FUNC(); CALL _HAL_INT_TIMER0_FUNC ; .line 34; interrupts.c INTCONbits.TMR0IF = 0; // clear flag BCF _INTCONbits, 2 _00387_DS_: MOVFF PREINC1, r0x00 MOVFF PREINC1, FSR2L MOVFF PREINC1, PCLATU MOVFF PREINC1, PCLATH MOVFF PREINC1, FSR0H MOVFF PREINC1, FSR0L MOVFF PREINC1, PRODH MOVFF PREINC1, PRODL MOVFF PREINC1, BSR MOVFF PREINC1, STATUS MOVFF PREINC1, WREG RETFIE ; ; Starting pCode block S_jgjh__SERIAL_writable code _SERIAL_writable: ; .line 143; serial.c bool SERIAL_writable(SERIAL_handle h) MOVFF FSR2L, POSTDEC1 MOVFF FSR1L, FSR2L MOVFF r0x00, POSTDEC1 MOVFF r0x01, POSTDEC1 MOVLW 0x02 MOVFF PLUSW2, r0x00 MOVLW 0x03 MOVFF PLUSW2, r0x01 ; .line 145; serial.c if(h==0) MOVF r0x00, W IORWF r0x01, W BNZ _00379_DS_ ; .line 147; serial.c if(usart_busy()) CALL _usart_busy MOVWF r0x00 MOVF r0x00, W BZ _00376_DS_ ; .line 149; serial.c return 0; // not writable CLRF WREG BRA _00380_DS_ _00376_DS_: ; .line 153; serial.c return 1; // writable MOVLW 0x01 BRA _00380_DS_ _00379_DS_: ; .line 157; serial.c return 0; CLRF WREG _00380_DS_: MOVFF PREINC1, r0x01 MOVFF PREINC1, r0x00 MOVFF PREINC1, FSR2L RETURN ; ; Starting pCode block S_jgjh__SERIAL_readable code _SERIAL_readable: ; .line 125; serial.c bool SERIAL_readable(SERIAL_handle h) MOVFF FSR2L, POSTDEC1 MOVFF FSR1L, FSR2L MOVFF r0x00, POSTDEC1 MOVFF r0x01, POSTDEC1 MOVLW 0x02 MOVFF PLUSW2, r0x00 MOVLW 0x03 MOVFF PLUSW2, r0x01 ; .line 127; serial.c if(h == 0) //uart MOVF r0x00, W IORWF r0x01, W BNZ _00356_DS_ ; .line 129; serial.c if(PIR1bits.RCIF)return 1; BTFSS _PIR1bits, 5 BRA _00353_DS_ MOVLW 0x01 BRA _00362_DS_ _00353_DS_: ; .line 130; serial.c else return 0; CLRF WREG BRA _00362_DS_ _00356_DS_: ; .line 132; serial.c if(h==1) //SPI MOVF r0x00, W XORLW 0x01 BNZ _00368_DS_ MOVF r0x01, W BZ _00369_DS_ _00368_DS_: BRA _00361_DS_ _00369_DS_: ; .line 134; serial.c if(SSPSTAT & 0x01) return 1; BTFSS _SSPSTAT, 0 BRA _00358_DS_ MOVLW 0x01 BRA _00362_DS_ _00358_DS_: ; .line 135; serial.c else return 0; CLRF WREG BRA _00362_DS_ _00361_DS_: ; .line 138; serial.c return 0; CLRF WREG _00362_DS_: MOVFF PREINC1, r0x01 MOVFF PREINC1, r0x00 MOVFF PREINC1, FSR2L RETURN ; ; Starting pCode block S_jgjh__SERIAL_write code _SERIAL_write: ; .line 112; serial.c void SERIAL_write(SERIAL_handle h,SERIAL_datatype *t, int n) MOVFF FSR2L, POSTDEC1 MOVFF FSR1L, FSR2L MOVFF r0x00, POSTDEC1 MOVFF r0x01, POSTDEC1 MOVFF r0x02, POSTDEC1 MOVFF r0x03, POSTDEC1 MOVFF r0x04, POSTDEC1 MOVFF r0x05, POSTDEC1 MOVFF r0x06, POSTDEC1 MOVFF r0x07, POSTDEC1 MOVFF r0x08, POSTDEC1 MOVFF r0x09, POSTDEC1 MOVFF r0x0a, POSTDEC1 MOVFF r0x0b, POSTDEC1 MOVLW 0x02 MOVFF PLUSW2, r0x00 MOVLW 0x03 MOVFF PLUSW2, r0x01 MOVLW 0x04 MOVFF PLUSW2, r0x02 MOVLW 0x05 MOVFF PLUSW2, r0x03 MOVLW 0x06 MOVFF PLUSW2, r0x04 MOVLW 0x07 MOVFF PLUSW2, r0x05 MOVLW 0x08 MOVFF PLUSW2, r0x06 ; .line 116; serial.c if(h==0 || h==1) // will spi pose a problem by overwriting previous data?. MOVF r0x00, W IORWF r0x01, W BZ _00343_DS_ MOVF r0x00, W XORLW 0x01 BNZ _00345_DS_ MOVF r0x01, W BZ _00343_DS_ _00345_DS_: BRA _00339_DS_ _00343_DS_: ; .line 118; serial.c for( i = 0; ibaud))/(ucon->baud)/4 - 1) <= 255) MOVFF r0x02, FSR0L MOVFF r0x03, PRODL MOVF r0x04, W CALL __gptrget2 MOVWF r0x05 MOVFF PRODL, r0x06 MOVF r0x06, W MOVWF POSTDEC1 MOVF r0x05, W MOVWF POSTDEC1 MOVLW 0x00 MOVWF POSTDEC1 MOVLW 0x02 MOVWF POSTDEC1 CALL __mulint MOVWF r0x07 MOVFF PRODL, r0x08 MOVLW 0x04 ADDWF FSR1L, F CLRF r0x09 CLRF r0x0a MOVLW 0x40 ADDWF r0x07, F MOVLW 0x4b ADDWFC r0x08, F MOVLW 0x4c ADDWFC r0x09, F MOVLW 0x00 ADDWFC r0x0a, F MOVFF r0x05, r0x0b MOVFF r0x06, r0x0c CLRF r0x0d CLRF r0x0e MOVF r0x0e, W MOVWF POSTDEC1 MOVF r0x0d, W MOVWF POSTDEC1 MOVF r0x0c, W MOVWF POSTDEC1 MOVF r0x0b, W MOVWF POSTDEC1 MOVF r0x0a, W MOVWF POSTDEC1 MOVF r0x09, W MOVWF POSTDEC1 MOVF r0x08, W MOVWF POSTDEC1 MOVF r0x07, W MOVWF POSTDEC1 CALL __divslong MOVWF r0x07 MOVFF PRODL, r0x08 MOVFF PRODH, r0x09 MOVFF FSR0L, r0x0a MOVLW 0x08 ADDWF FSR1L, F MOVLW 0x00 MOVWF POSTDEC1 MOVLW 0x00 MOVWF POSTDEC1 MOVLW 0x00 MOVWF POSTDEC1 MOVLW 0x04 MOVWF POSTDEC1 MOVF r0x0a, W MOVWF POSTDEC1 MOVF r0x09, W MOVWF POSTDEC1 MOVF r0x08, W MOVWF POSTDEC1 MOVF r0x07, W MOVWF POSTDEC1 CALL __divslong MOVWF r0x07 MOVFF PRODL, r0x08 MOVFF PRODH, r0x09 MOVFF FSR0L, r0x0a MOVLW 0x08 ADDWF FSR1L, F MOVLW 0xff ADDWF r0x07, F MOVLW 0xff ADDWFC r0x08, F MOVLW 0xff ADDWFC r0x09, F MOVLW 0xff ADDWFC r0x0a, F MOVF r0x0a, W ADDLW 0x80 ADDLW 0x80 BNZ _00289_DS_ MOVLW 0x00 SUBWF r0x09, W BNZ _00289_DS_ MOVLW 0x01 SUBWF r0x08, W BNZ _00289_DS_ MOVLW 0x00 SUBWF r0x07, W _00289_DS_: BC _00274_DS_ ; .line 20; serial.c USART_BRGH_HIGH, BAUD_SPBRG); MOVF r0x08, W MOVWF POSTDEC1 MOVF r0x07, W MOVWF POSTDEC1 MOVLW 0x3c CALL _usart_open MOVLW 0x02 ADDWF FSR1L, F BRA _00275_DS_ _00274_DS_: ; .line 25; serial.c BAUD_SPBRG = (INSTR_FREQ+8*ucon->baud)/ucon->baud/16 - 1; MOVF r0x06, W MOVWF POSTDEC1 MOVF r0x05, W MOVWF POSTDEC1 MOVLW 0x00 MOVWF POSTDEC1 MOVLW 0x08 MOVWF POSTDEC1 CALL __mulint MOVWF r0x05 MOVFF PRODL, r0x06 MOVLW 0x04 ADDWF FSR1L, F CLRF r0x09 CLRF r0x0a MOVLW 0x40 ADDWF r0x05, F MOVLW 0x4b ADDWFC r0x06, F MOVLW 0x4c ADDWFC r0x09, F MOVLW 0x00 ADDWFC r0x0a, F MOVF r0x0e, W MOVWF POSTDEC1 MOVF r0x0d, W MOVWF POSTDEC1 MOVF r0x0c, W MOVWF POSTDEC1 MOVF r0x0b, W MOVWF POSTDEC1 MOVF r0x0a, W MOVWF POSTDEC1 MOVF r0x09, W MOVWF POSTDEC1 MOVF r0x06, W MOVWF POSTDEC1 MOVF r0x05, W MOVWF POSTDEC1 CALL __divslong MOVWF r0x05 MOVFF PRODL, r0x06 MOVFF PRODH, r0x09 MOVFF FSR0L, r0x0a MOVLW 0x08 ADDWF FSR1L, F MOVLW 0x00 MOVWF POSTDEC1 MOVLW 0x00 MOVWF POSTDEC1 MOVLW 0x00 MOVWF POSTDEC1 MOVLW 0x10 MOVWF POSTDEC1 MOVF r0x0a, W MOVWF POSTDEC1 MOVF r0x09, W MOVWF POSTDEC1 MOVF r0x06, W MOVWF POSTDEC1 MOVF r0x05, W MOVWF POSTDEC1 CALL __divslong MOVWF r0x05 MOVFF PRODL, r0x06 MOVFF PRODH, r0x09 MOVFF FSR0L, r0x0a MOVLW 0x08 ADDWF FSR1L, F MOVLW 0xff ADDWF r0x05, F MOVLW 0xff ADDWFC r0x06, F MOVLW 0xff ADDWFC r0x09, F MOVLW 0xff ADDWFC r0x0a, F MOVF r0x05, W MOVWF r0x07 MOVF r0x06, W MOVWF r0x08 ; .line 31; serial.c USART_BRGH_LOW, BAUD_SPBRG); MOVF r0x08, W MOVWF POSTDEC1 MOVF r0x07, W MOVWF POSTDEC1 MOVLW 0x2c CALL _usart_open MOVLW 0x02 ADDWF FSR1L, F _00275_DS_: ; .line 34; serial.c usart_putc(13); MOVLW 0x0d CALL _usart_putc ; .line 35; serial.c RCSTAbits.SPEN = 1; //enable uart BSF _RCSTAbits, 7 ; .line 36; serial.c RCSTAbits.CREN = 1; // continous receive enable BSF _RCSTAbits, 4 ; .line 37; serial.c return 1; CLRF PRODL MOVLW 0x01 BRA _00283_DS_ _00277_DS_: ; .line 42; serial.c if(h==1) // SPI MOVF r0x00, W XORLW 0x01 BNZ _00290_DS_ MOVF r0x01, W BZ _00291_DS_ _00290_DS_: BRA _00282_DS_ _00291_DS_: ; .line 45; serial.c if(ucon->mstr_slv) MOVLW 0x04 ADDWF r0x02, F MOVLW 0x00 ADDWFC r0x03, F MOVLW 0x00 ADDWFC r0x04, F MOVFF r0x02, FSR0L MOVFF r0x03, PRODL MOVF r0x04, W CALL __gptrget1 MOVWF r0x02 MOVF r0x02, W BZ _00279_DS_ ; .line 48; serial.c TRISCbits.TRISC5 = 0; // serial data out SDO BCF _TRISCbits, 5 ; .line 49; serial.c TRISCbits.TRISC4 = 1; //SDI BSF _TRISCbits, 4 ; .line 50; serial.c TRISCbits.TRISC3 = 0; // SCK BCF _TRISCbits, 3 ; .line 52; serial.c SSPSTAT = 0; // set data sampled at middle & CKE = 0 CLRF _SSPSTAT ; .line 53; serial.c SSPCON1 = 0x21; // Master mode Fosc/16, enable SPI MOVLW 0x21 MOVWF _SSPCON1 BRA _00280_DS_ _00279_DS_: ; .line 58; serial.c TRISCbits.TRISC5 = 0; // serial data out SDO BCF _TRISCbits, 5 ; .line 59; serial.c TRISCbits.TRISC4 = 1; //SDI BSF _TRISCbits, 4 ; .line 60; serial.c TRISCbits.TRISC3 = 1; // SCK set as input for slave BSF _TRISCbits, 3 ; .line 62; serial.c SSPSTAT = 0; // set data sampled at middle & CKE = 0 CLRF _SSPSTAT ; .line 63; serial.c SSPCON1 = 0x25; // Slave mode,SS disabled enable SPI MOVLW 0x25 MOVWF _SSPCON1 _00280_DS_: ; .line 66; serial.c return 1; CLRF PRODL MOVLW 0x01 BRA _00283_DS_ _00282_DS_: ; .line 72; serial.c return 0; // not able to find the correct serial channel CLRF PRODL CLRF WREG _00283_DS_: MOVFF PREINC1, r0x0e MOVFF PREINC1, r0x0d MOVFF PREINC1, r0x0c MOVFF PREINC1, r0x0b MOVFF PREINC1, r0x0a MOVFF PREINC1, r0x09 MOVFF PREINC1, r0x08 MOVFF PREINC1, r0x07 MOVFF PREINC1, r0x06 MOVFF PREINC1, r0x05 MOVFF PREINC1, r0x04 MOVFF PREINC1, r0x03 MOVFF PREINC1, r0x02 MOVFF PREINC1, r0x01 MOVFF PREINC1, r0x00 MOVFF PREINC1, FSR2L RETURN ; ; Starting pCode block S_jgjh__HAL_write_eeprom_byte code _HAL_write_eeprom_byte: ; .line 14; eeprom.c void HAL_write_eeprom_byte(uint8_t addr, uint8_t dat) MOVFF FSR2L, POSTDEC1 MOVFF FSR1L, FSR2L MOVFF r0x00, POSTDEC1 MOVLW 0x02 MOVFF PLUSW2, r0x00 MOVLW 0x03 MOVFF PLUSW2, _EEDATA ; .line 17; eeprom.c EEADR = addr; MOVFF r0x00, _EEADR ; .line 19; eeprom.c EECON1bits.EEPGD = 0; BCF _EECON1bits, 7 ; .line 20; eeprom.c EECON1bits.CFGS = 0; BCF _EECON1bits, 6 ; .line 21; eeprom.c EECON1bits.WREN = 1; // enable writes to data EEPROM BSF _EECON1bits, 2 ; .line 22; eeprom.c INTCONbits.GIE = 0; // disable interrupts BCF _INTCONbits, 7 ; .line 23; eeprom.c EECON2 = 0x55; MOVLW 0x55 MOVWF _EECON2 ; .line 24; eeprom.c EECON2 = 0x0AA; MOVLW 0xaa MOVWF _EECON2 ; .line 25; eeprom.c EECON1bits.WR = 1; // start writing BSF _EECON1bits, 1 _00257_DS_: ; .line 26; eeprom.c while(EECON1bits.WR){ BTFSS _EECON1bits, 1 BRA _00259_DS_ nop BRA _00257_DS_ _00259_DS_: ; .line 28; eeprom.c if(EECON1bits.WRERR){ BTFSS _EECON1bits, 3 BRA _00267_DS_ ; .line 29; eeprom.c usart_putc('E'); MOVLW 0x45 CALL _usart_putc _00260_DS_: ; .line 30; eeprom.c while(usart_busy()); CALL _usart_busy MOVWF r0x00 MOVF r0x00, W BNZ _00260_DS_ ; .line 31; eeprom.c usart_putc('R'); MOVLW 0x52 CALL _usart_putc _00263_DS_: ; .line 32; eeprom.c while(usart_busy()); CALL _usart_busy MOVWF r0x00 MOVF r0x00, W BNZ _00263_DS_ ; .line 33; eeprom.c usart_putc('R'); MOVLW 0x52 CALL _usart_putc _00267_DS_: ; .line 36; eeprom.c EECON1bits.WREN = 0; BCF _EECON1bits, 2 ; .line 37; eeprom.c INTCONbits.GIE = 1; // enable interrupts BSF _INTCONbits, 7 MOVFF PREINC1, r0x00 MOVFF PREINC1, FSR2L RETURN ; ; Starting pCode block S_jgjh__HAL_read_eeprom_byte code _HAL_read_eeprom_byte: ; .line 4; eeprom.c uint8_t HAL_read_eeprom_byte(uint8_t addr) MOVFF FSR2L, POSTDEC1 MOVFF FSR1L, FSR2L MOVLW 0x02 MOVFF PLUSW2, _EEADR ; .line 7; eeprom.c EECON1bits.CFGS = 0; BCF _EECON1bits, 6 ; .line 8; eeprom.c EECON1bits.EEPGD = 0; BCF _EECON1bits, 7 ; .line 9; eeprom.c EECON1bits.RD = 1; BSF _EECON1bits, 0 ; .line 10; eeprom.c return EEDATA; MOVF _EEDATA, W MOVFF PREINC1, FSR2L RETURN ; ; Starting pCode block S_jgjh__EEPROM_memset code _EEPROM_memset: ; .line 29; eeprom.h static uint8_t EEPROM_memset( uint8_t addr, void *src, uint8_t len ) { MOVFF FSR2L, POSTDEC1 MOVFF FSR1L, FSR2L MOVFF r0x00, POSTDEC1 MOVFF r0x01, POSTDEC1 MOVFF r0x02, POSTDEC1 MOVFF r0x03, POSTDEC1 MOVFF r0x04, POSTDEC1 MOVFF r0x05, POSTDEC1 MOVFF r0x06, POSTDEC1 MOVFF r0x07, POSTDEC1 MOVLW 0x02 MOVFF PLUSW2, r0x00 MOVLW 0x03 MOVFF PLUSW2, r0x01 MOVLW 0x04 MOVFF PLUSW2, r0x02 MOVLW 0x05 MOVFF PLUSW2, r0x03 MOVLW 0x06 MOVFF PLUSW2, r0x04 ; .line 31; eeprom.h for (i=0; iID, msg->buf, msg->len, MOVFF r0x00, FSR0L MOVFF r0x01, PRODL MOVF r0x02, W CALL __gptrget2 MOVWF r0x03 MOVFF PRODL, r0x04 CLRF r0x05 CLRF r0x06 MOVF r0x00, W ADDLW 0x03 MOVWF r0x07 MOVLW 0x00 ADDWFC r0x01, W MOVWF r0x08 MOVLW 0x00 ADDWFC r0x02, W MOVWF r0x09 MOVLW 0x02 ADDWF r0x00, F MOVLW 0x00 ADDWFC r0x01, F MOVLW 0x00 ADDWFC r0x02, F MOVFF r0x00, FSR0L MOVFF r0x01, PRODL MOVF r0x02, W CALL __gptrget1 MOVWF r0x00 ; .line 78; can.c ECAN_TX_PRIORITY_0 & ECAN_TX_STD_FRAME & ECAN_TX_NO_RTR_FRAME); MOVLW 0x00 MOVWF POSTDEC1 MOVF r0x00, W MOVWF POSTDEC1 MOVF r0x09, W MOVWF POSTDEC1 MOVF r0x08, W MOVWF POSTDEC1 MOVF r0x07, W MOVWF POSTDEC1 MOVF r0x06, W MOVWF POSTDEC1 MOVF r0x05, W MOVWF POSTDEC1 MOVF r0x04, W MOVWF POSTDEC1 MOVF r0x03, W MOVWF POSTDEC1 CALL _ECANSendMessage MOVWF r0x00 MOVLW 0x09 ADDWF FSR1L, F CLRF r0x01 ; .line 80; can.c if (rc) MOVF r0x00, W IORWF r0x01, W BZ _00187_DS_ ; .line 81; can.c CAN_status1.tx++; MOVFF _CAN_status1, r0x02 INCF r0x02, F MOVF r0x02, W BANKSEL _CAN_status1 MOVWF _CAN_status1, B BRA _00188_DS_ _00187_DS_: ; .line 83; can.c CAN_status1.txError++; MOVFF (_CAN_status1 + 1), r0x02 INCF r0x02, F MOVF r0x02, W BANKSEL (_CAN_status1 + 1) MOVWF (_CAN_status1 + 1), B _00188_DS_: ; .line 85; can.c return rc; MOVFF r0x01, PRODL MOVF r0x00, W MOVFF PREINC1, r0x09 MOVFF PREINC1, r0x08 MOVFF PREINC1, r0x07 MOVFF PREINC1, r0x06 MOVFF PREINC1, r0x05 MOVFF PREINC1, r0x04 MOVFF PREINC1, r0x03 MOVFF PREINC1, r0x02 MOVFF PREINC1, r0x01 MOVFF PREINC1, r0x00 MOVFF PREINC1, FSR2L RETURN ; ; Starting pCode block S_jgjh__CAN_recv code _CAN_recv: ; .line 43; can.c int CAN_recv( struct CAN_msg *msg ) { MOVFF FSR2L, POSTDEC1 MOVFF FSR1L, FSR2L MOVFF r0x00, POSTDEC1 MOVFF r0x01, POSTDEC1 MOVFF r0x02, POSTDEC1 MOVFF r0x03, POSTDEC1 MOVFF r0x04, POSTDEC1 MOVFF r0x05, POSTDEC1 MOVFF r0x06, POSTDEC1 MOVFF r0x07, POSTDEC1 MOVFF r0x08, POSTDEC1 MOVFF r0x09, POSTDEC1 MOVFF r0x0a, POSTDEC1 MOVFF r0x0b, POSTDEC1 MOVFF r0x0c, POSTDEC1 MOVFF r0x0d, POSTDEC1 MOVFF r0x0e, POSTDEC1 MOVLW 0x02 MOVFF PLUSW2, r0x00 MOVLW 0x03 MOVFF PLUSW2, r0x01 MOVLW 0x04 MOVFF PLUSW2, r0x02 ; .line 55; can.c if (!ECANReceiveMessage ((unsigned long *)&temp, msg->buf, &msg->len, &flags)) MOVLW HIGH(_CAN_recv_temp_1_1) MOVWF r0x04 MOVLW LOW(_CAN_recv_temp_1_1) MOVWF r0x03 MOVLW 0x80 MOVWF r0x05 MOVF r0x00, W ADDLW 0x03 MOVWF r0x06 MOVLW 0x00 ADDWFC r0x01, W MOVWF r0x07 MOVLW 0x00 ADDWFC r0x02, W MOVWF r0x08 MOVF r0x00, W ADDLW 0x02 MOVWF r0x09 MOVLW 0x00 ADDWFC r0x01, W MOVWF r0x0a MOVLW 0x00 ADDWFC r0x02, W MOVWF r0x0b MOVLW HIGH(_CAN_recv_flags_1_1) MOVWF r0x0d MOVLW LOW(_CAN_recv_flags_1_1) MOVWF r0x0c MOVLW 0x80 MOVWF r0x0e MOVF r0x0e, W MOVWF POSTDEC1 MOVF r0x0d, W MOVWF POSTDEC1 MOVF r0x0c, W MOVWF POSTDEC1 MOVF r0x0b, W MOVWF POSTDEC1 MOVF r0x0a, W MOVWF POSTDEC1 MOVF r0x09, W MOVWF POSTDEC1 MOVF r0x08, W MOVWF POSTDEC1 MOVF r0x07, W MOVWF POSTDEC1 MOVF r0x06, W MOVWF POSTDEC1 MOVF r0x05, W MOVWF POSTDEC1 MOVF r0x04, W MOVWF POSTDEC1 MOVF r0x03, W MOVWF POSTDEC1 CALL _ECANReceiveMessage MOVWF r0x03 MOVLW 0x0c ADDWF FSR1L, F MOVF r0x03, W BNZ _00170_DS_ ; .line 56; can.c return 0; CLRF PRODL CLRF WREG BRA _00175_DS_ _00170_DS_: BANKSEL _CAN_recv_temp_1_1 ; .line 57; can.c msg->ID = (uint16_t) temp; MOVF _CAN_recv_temp_1_1, W, B MOVWF r0x03 BANKSEL (_CAN_recv_temp_1_1 + 1) MOVF (_CAN_recv_temp_1_1 + 1), W, B MOVWF r0x04 MOVFF r0x03, POSTDEC1 MOVFF r0x04, PRODH MOVFF r0x00, FSR0L MOVFF r0x01, PRODL MOVF r0x02, W CALL __gptrput2 ; .line 58; can.c CAN_status1.rx ++; MOVFF (_CAN_status1 + 2), r0x03 INCF r0x03, F MOVF r0x03, W BANKSEL (_CAN_status1 + 2) MOVWF (_CAN_status1 + 2), B BANKSEL _CAN_recv_flags_1_1 ; .line 60; can.c if (flags & (ECAN_RX_XTD_FRAME | ECAN_RX_RTR_FRAME)) { // don't accept these strange things. MOVF _CAN_recv_flags_1_1, W, B ANDLW 0x60 BZ _00172_DS_ ; .line 61; can.c CAN_status1.exotic++; MOVFF (_CAN_status1 + 4), r0x03 INCF r0x03, F MOVF r0x03, W BANKSEL (_CAN_status1 + 4) MOVWF (_CAN_status1 + 4), B ; .line 62; can.c return -1; SETF PRODL SETF WREG BRA _00175_DS_ _00172_DS_: BANKSEL _CAN_recv_flags_1_1 ; .line 64; can.c if (flags & ECAN_RX_OVERFLOW) { // it's not clear what this flag means, but count it. BTFSS _CAN_recv_flags_1_1, 3, B BRA _00174_DS_ ; .line 65; can.c CAN_status1.overflow++; MOVFF (_CAN_status1 + 3), r0x03 INCF r0x03, F MOVF r0x03, W BANKSEL (_CAN_status1 + 3) MOVWF (_CAN_status1 + 3), B ; .line 66; can.c return -2; SETF PRODL MOVLW 0xfe BRA _00175_DS_ _00174_DS_: ; .line 69; can.c return msg->len; MOVLW 0x02 ADDWF r0x00, F MOVLW 0x00 ADDWFC r0x01, F MOVLW 0x00 ADDWFC r0x02, F MOVFF r0x00, FSR0L MOVFF r0x01, PRODL MOVF r0x02, W CALL __gptrget1 MOVWF r0x00 CLRF r0x01 MOVFF r0x01, PRODL MOVF r0x00, W _00175_DS_: MOVFF PREINC1, r0x0e MOVFF PREINC1, r0x0d MOVFF PREINC1, r0x0c MOVFF PREINC1, r0x0b MOVFF PREINC1, r0x0a MOVFF PREINC1, r0x09 MOVFF PREINC1, r0x08 MOVFF PREINC1, r0x07 MOVFF PREINC1, r0x06 MOVFF PREINC1, r0x05 MOVFF PREINC1, r0x04 MOVFF PREINC1, r0x03 MOVFF PREINC1, r0x02 MOVFF PREINC1, r0x01 MOVFF PREINC1, r0x00 MOVFF PREINC1, FSR2L RETURN ; ; Starting pCode block S_jgjh__CAN_init code _CAN_init: ; .line 30; can.c int CAN_init( void ) { MOVFF FSR2L, POSTDEC1 MOVFF FSR1L, FSR2L MOVFF r0x00, POSTDEC1 MOVFF r0x01, POSTDEC1 MOVFF r0x02, POSTDEC1 MOVFF r0x03, POSTDEC1 ; .line 35; can.c ECANInitialize(); CALL _ECANInitialize ; .line 37; can.c for (k = 0; k> 8); MOVF r0x01, W MOVWF r0x02 CLRF r0x03 MOVF r0x02, W MOVWF _TMR0H ; .line 33; timer.c TMR0L = (unsigned char)(v); MOVF r0x00, W MOVWF _TMR0L MOVFF PREINC1, r0x03 MOVFF PREINC1, r0x02 MOVFF PREINC1, r0x01 MOVFF PREINC1, r0x00 MOVFF PREINC1, FSR2L RETURN ; ; Starting pCode block S_jgjh__TIMER_setup code _TIMER_setup: ; .line 3; timer.c bool TIMER_setup( TIMER_handle t, struct TIMER_config *cfg ) MOVFF FSR2L, POSTDEC1 MOVFF FSR1L, FSR2L MOVFF r0x00, POSTDEC1 MOVFF r0x01, POSTDEC1 MOVFF r0x02, POSTDEC1 MOVFF r0x03, POSTDEC1 MOVLW 0x02 MOVFF PLUSW2, r0x00 MOVLW 0x03 MOVFF PLUSW2, r0x01 MOVLW 0x04 MOVFF PLUSW2, r0x02 MOVLW 0x05 MOVFF PLUSW2, r0x03 ; .line 5; timer.c switch (t) { MOVLW 0x03 SUBWF r0x00, W BTFSC STATUS, 0 BRA _00111_DS_ MOVFF r0x04, POSTDEC1 MOVFF r0x05, POSTDEC1 CLRF r0x05 RLCF r0x00, W RLCF r0x05, F RLCF WREG, W RLCF r0x05, F ANDLW 0xfc MOVWF r0x04 MOVLW UPPER(_00117_DS_) MOVWF PCLATU MOVLW HIGH(_00117_DS_) MOVWF PCLATH MOVLW LOW(_00117_DS_) ADDWF r0x04, F MOVF r0x05, W ADDWFC PCLATH, F BTFSC STATUS, 0 INCF PCLATU, F MOVF r0x04, W MOVFF PREINC1, r0x05 MOVFF PREINC1, r0x04 MOVWF PCL _00117_DS_: GOTO _00105_DS_ GOTO _00111_DS_ GOTO _00111_DS_ _00105_DS_: ; .line 7; timer.c if(cfg->scaler <=7) INCF r0x01, F BTFSC STATUS, 0 INCF r0x02, F BTFSC STATUS, 0 INCF r0x03, F MOVFF r0x01, FSR0L MOVFF r0x02, PRODL MOVF r0x03, W CALL __gptrget1 MOVWF r0x00 MOVLW 0x08 SUBWF r0x00, W BC _00107_DS_ ; .line 9; timer.c T0CON= 0; /* clear all bits*/ CLRF _T0CON ; .line 12; timer.c T0CON = T0CON | 0x80 | (cfg->scaler); MOVLW 0x80 IORWF _T0CON, W MOVWF r0x01 MOVF r0x00, W IORWF r0x01, W MOVWF _T0CON ; .line 13; timer.c return 1; MOVLW 0x01 BRA _00112_DS_ _00107_DS_: ; .line 16; timer.c return 0; CLRF WREG ; .line 20; timer.c break; BRA _00112_DS_ _00111_DS_: ; .line 27; timer.c return 0; CLRF WREG _00112_DS_: MOVFF PREINC1, r0x03 MOVFF PREINC1, r0x02 MOVFF PREINC1, r0x01 MOVFF PREINC1, r0x00 MOVFF PREINC1, FSR2L RETURN ; Statistics: ; code size: 4442 (0x115a) bytes ( 3.39%) ; 2221 (0x08ad) words ; udata size: 24 (0x0018) bytes ( 0.62%) ; access size: 18 (0x0012) bytes end